Agilex™ 7 FPGA – AN901: Implementing Synchronized ADC Dual Link Design with JESD204C RX IP Core Design Example - This application note provides guidelines to scale up the single link in the JESD204C Altera® FPGAs IP core design example generated from the Quartus® Prime software to handle a multipoint link system. A single link in JESD204C has one or more high-speed transceiver lanes or channels. - 2022-12-12

Version

22.3.0