Stratix® 10 FPGA – AN804: Implementing Synchronized ADC Multi-Link Design with JESD204B RX IP Core - This design example contains the sample files for the synchronized analog-to-digital (ADC) Stratix® 10 FPGA multi-link design for synthesis and simulation. - 2017-12-26
- Version
- 17.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Stratix Families > Stratix 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown