Arria® 10 FPGA – AN803: Implementing an Unsynchronized ADC Multi-Link Design with JESD204B RX Altera® FPGAs IP Core Design Example - This design example contains the sample files of the unsynchronized analog-to-digital converter (ADC) Arria® 10 FPGA multi-link design for synthesis and simulation. - 2018-01-10

Version

17.1.0