Arria® 10 FPGA – AN803: Implementing a Synchronized ADC Multi-Link Design with JESD204B RX Altera® FPGAs IP Core Design Example - This design example contains the sample files of the synchronized analog-to-digital converter (ADC) Arria® 10 FPGA multi-link design for synthesis and simulation. - 2018-01-07
- Version
- 17.1.0
- Product Type
- Device Families > Arria Families > Arria 10
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown