Stratix® 10 FPGA – AN 888: PHY Lite for Parallel Interface with Dynamic Reconfiguration for Altera® Devices Reference Design - This reference design demonstrates the usage of dynamic reconfiguration features using the PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP cores. Two instances of PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopbacked using the HiLo loopback card. One PHY Lite instance is configured as a transmitter and the other PHY Lite instance is configured as a receiver. - 2019-05-06

Version

19.1.0