Arria® 10 FPGA – AN 887: PHY Lite for Parallel Interface with Dynamic Reconfiguration for Altera® Devices Reference Design - The PHY Lite for Parallel Interfaces Altera® FPGAs IP core for Arria® 10 FPGAs has a per-bit calibration capability that is used to calibrate each DQ pin delay to achieve maximum performance. When a large amount of DQ pins are used on a high-speed transfer, it is very likely that most have a narrower passing window. This limits the maximum performance of the system, as well as the possibility of data corruption. - 2019-04-26

Version

19.1.0