MAX® 10 FPGA – ADC Data Capture with the Nios® II Processor Design Example - In this design example you will implement the MAX® 10 FPGA analog-to-digital converter (ADC) hard IP. You will replace the simple hardware driver with a Nios® II processor system. Note that this is a design extracted from Arrow's DECA workshop series of labs. - 2016-04-28

Version

16.0.0