MAX® 10 FPGA – ADC Data Capture with Hardware Streaming Using ADC Toolkit Display Design Example - In this design example, you will implement the MAX® 10 FPGA analog-to-digital converter (ADC) hard intellectual property (IP) core using hardware-only streaming. Note that this is a design extracted from Arrow's DECA workshop series of labs. - 2016-04-28
- Version
- 16.0.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Device Families > MAX Families > MAX 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown