MAX® 10 FPGA – Accelerated Nios® II/e Processor Tiny Embedded System Design Example - This tutorial describes a simple reference design for accelerating the Nios® II/e processor using Synaptic Labs' system cache, targeted specifically to MAX® 10 FPGAs. It also features Arduino-style key components and pin headers, such as PIO and I2C interfaces. In addition, it supports 16 Mbyte HyperRAM and 64 Mbyte HyperFlash memories. The total embedded system fits in the smallest 2K MAX® 10 FPGA. This reference design can be easily modified for other development boards and other Altera® FPGAs families. Note: This tutorial requires the Synaptic Labs HyperFlash Programmer. Contact Synaptic Labs for more info. Includes a free trial IP. - 2017-09-29

Version

17.0.0