Cyclone® 10 LP FPGA – Accelerated Nios® II/e Embedded Processor System Design Example - This tutorial describes a simple reference design for Synaptic Laboratories Ltd's HyperBus Memory Controller (HBMC) intellectual property (IP) core and system cache for accelerating the Nios® II/e processor, targeted specifically on the Cyclone® 10 LP evaluation board. It also features Arduino-style key components and pin headers, such as PIO, I2C, and SPI interfaces. In addition, it supports 16 Mbyte HyperRAM and 8 Mbyte EPCQ memories. The total embedded system fits in the smallest Cyclone® 10 FPGA. This reference design can be easily modified for other development boards and Altera® FPGAs families. Includes a free trial IP. - 2017-09-29

Version

17.0.0