Stratix® V FPGA – 40 Gbps Ethernet MACPHY IP Using QSFP Hardware Demo Design - This hardware demo design demonstrates the operation of the 40-Gbps Ethernet MAC and PHY Altera® FPGAs IP solution on a Stratix® V device. This design provides a flexible test and demonstration platform that effectively controls, tests, and monitors 40 Gbps Ethernet packets using internal serial physical media attachment (PMA) loopback and external optical loopback MAC client-side RX to TX parallel loopback. - 2019-06-06
- Version
- 17.1.0
- Product Type
- Device Families > Stratix Families > Stratix V
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Standard Edition
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown