Stratix® 10 FPGA – 1G / 2.5G Ethernet Design Example - This design example demonstrates the 1G/2.5G Ethernet IP solution for the Stratix® 10 device family using the Low Latency Ethernet 10G MAC (1G/2.5G mode) and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Altera® FPGAs IP cores on the Stratix® 10 GX FPGA Signal Integrity Development Board with small form factor pluggable plus (SFP+). - 2017-12-11
- Version
- 17.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Stratix Families > Stratix 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown