Stratix® 10 FPGA – 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design - This application note showcases the synchronization of two x8-lane Stratix® 10 FPGA JESD204B RX IP cores interoperating with the 12-bit, 16-lane TI ADC12DJ3200 Evaluation Module (EVM) running at 6.4 Gbps per lane connected through a FMC+ port A connector. - 2017-11-28
- Version
- 17.1.0
- Product Type
- Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
- Device Families > Stratix Families > Stratix 10
- Resource Type
- Developer Resources > Example Resources > Example Designs > System Example Designs
- Source Name
- Markdown