Intel® Quartus® Prime Integrated Synthesis - Intel® Quartus® Prime Integrated Synthesis - 2018-09-24

Source Name: DITA

1. Intel® Quartus® Prime Integrated Synthesis
1.1. Design Flow
1.1.1. Intel® Quartus® Prime Integrated Synthesis Design and Compilation Flow
1.1.1.1. Factors Affecting Compilation Results
1.2. Language Support
1.2.1. Verilog and SystemVerilog Synthesis Support
1.2.1.1. Verilog HDL Configuration
1.2.1.1.1. Configuration Syntax
1.2.1.1.2. Hierarchical Design Configurations
1.2.1.1.3. Suffix :config
1.2.1.2. SystemVerilog Support
1.2.1.3. Initial Constructs and Memory System Tasks
1.2.1.4. Verilog HDL Macros
1.2.1.4.1. Setting a Verilog HDL Macro Default Value in the Intel® Quartus® Prime Software
1.2.1.4.2. Setting a Verilog HDL Macro Default Value on the Command Line
1.2.2. VHDL Synthesis Support
1.2.2.1. Intel® Quartus® Prime Support for VHDL 2008
1.2.2.2. VHDL Standard Libraries and Packages
1.2.2.3. VHDL wait Constructs
1.2.3. AHDL Support
1.2.4. Schematic Design Entry Support
1.2.5. State Machine Editor
1.2.6. Design Libraries
1.2.6.1. Specifying a Destination Library Name in the Settings Dialog Box
1.2.6.2. Specifying a Destination Library Name in the Intel® Quartus® Prime Settings File or with Tcl
1.2.6.3. Specifying a Destination Library Name in a VHDL File
1.2.6.4. Mapping a VHDL Instance to an Entity in a Specific Library
1.2.6.4.1. Direct Entity Instantiation
1.2.6.4.2. Component Instantiation—Explicit Binding Instantiation
1.2.6.4.3. Component Instantiation—Default Binding
1.2.7. Using Parameters/Generics
1.2.7.1. Setting Default Parameter Values and BDF Instance Parameter Values
1.2.7.2. Passing Parameters Between Two Design Languages
1.3. Incremental Compilation
1.3.1. Partitions for Preserving Hierarchical Boundaries
1.3.2. Parallel Synthesis
1.3.3. Intel® Quartus® Prime Exported Partition File as Source
1.4. Intel® Quartus® Prime Synthesis Options
1.4.1. Setting Synthesis Options
1.4.1.1. Intel® Quartus® Prime Logic Options
1.4.1.2. Synthesis Attributes
1.4.1.2.1. Synthesis Attributes in Verilog-1995
1.4.1.2.2. Synthesis Attributes in Verilog-2001
1.4.1.2.3. Synthesis Attributes in VHDL
1.4.1.3. Synthesis Directives
1.4.2. Optimization Technique
1.4.3. Auto Gated Clock Conversion
1.4.4. Enabling Timing-Driven Synthesis
1.4.5. SDC Constraint Protection
1.4.6. PowerPlay Power Optimization
1.4.7. Limiting Resource Usage in Partitions
1.4.7.1. Creating LogicLock Regions
1.4.7.2. Using Assignments to Limit the Number of RAM and DSP Blocks
1.4.8. Restructure Multiplexers
1.4.9. Synthesis Effort
1.4.10. Fitter Intial Placement Seed
1.4.11. State Machine Processing
1.4.11.1. Manually Specifying State Assignments Using the syn_encoding Attribute
1.4.11.2. Manually Specifying Enumerated Types Using the enum_encoding Attribute
1.4.12. Safe State Machine
1.4.13. Power-Up Level
1.4.13.1. Inferred Power-Up Levels
1.4.14. Power-Up Don’t Care
1.4.15. Remove Duplicate Registers
1.4.16. Preserve Registers
1.4.17. Disable Register Merging/Don’t Merge Register
1.4.18. Noprune Synthesis Attribute/Preserve Fan-out Free Register Node
1.4.19. Keep Combinational Node/Implement as Output of Logic Cell
1.4.20. Disabling Synthesis Netlist Optimizations with dont_retime Attribute
1.4.21. Disabling Synthesis Netlist Optimizations with dont_replicate Attribute
1.4.22. Maximum Fan-Out
1.4.23. Controlling Clock Enable Signals with Auto Clock Enable Replacement and direct_enable
1.5. Inferring Multiplier, DSP, and Memory Functions from HDL Code
1.5.1. Multiply-Accumulators and Multiply-Adders
1.5.2. Shift Registers
1.5.3. RAM and ROM
1.5.4. Resource Aware RAM, ROM, and Shift-Register Inference
1.5.5. Auto RAM to Logic Cell Conversion
1.5.6. RAM Style and ROM Style—for Inferred Memory
1.5.7. RAM Style Attribute—For Shift Registers Inference
1.5.8. Disabling Add Pass-Through Logic to Inferred RAMs no_rw_check Attribute
1.5.9. RAM Initialization File—for Inferred Memory
1.5.10. Multiplier Style—for Inferred Multipliers
1.5.11. Full Case Attribute
1.5.12. Parallel Case
1.5.13. Translate Off and On / Synthesis Off and On
1.5.14. Ignore translate_off and synthesis_off Directives
1.5.15. Read Comments as HDL
1.5.16. Use I/O Flipflops
1.5.17. Specifying Pin Locations with chip_pin
1.5.18. Using altera_attribute to Set Intel® Quartus® Prime Logic Options
1.6. Analyzing Synthesis Results
1.6.1. Analysis & Synthesis Section of the Compilation Report
1.6.2. Project Navigator
1.6.2.1. Upgrade IP Components Dialog Box
1.7. Analyzing and Controlling Synthesis Messages
1.7.1. Intel® Quartus® Prime Messages
1.7.2. VHDL and Verilog HDL Messages
1.7.2.1. Setting the HDL Message Level
1.7.2.2. Enabling or Disabling Specific HDL Messages by Module/Entity
1.8. Node-Naming Conventions in Intel® Quartus® Prime Integrated Synthesis
1.8.1. Hierarchical Node-Naming Conventions
1.8.2. Node-Naming Conventions for Registers (DFF or D Flipflop Atoms)
1.8.3. Register Changes During Synthesis
1.8.3.1. Synthesis and Fitting Optimizations
1.8.3.2. State Machines
1.8.3.3. Inferred Adder-Subtractors, Shift Registers, Memory, and DSP Functions
1.8.3.4. Packed Input and Output Registers of RAM and DSP Blocks
1.8.4. Preserving Register Names
1.8.5. Node-Naming Conventions for Combinational Logic Cells
1.8.6. Preserving Combinational Logic Names
1.9. Scripting Support
1.9.1. Adding an HDL File to a Project and Setting the HDL Version
1.9.2. Assigning a Pin
1.9.3. Creating Design Partitions for Incremental Compilation
1.10. Document Revision History

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