Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Best Practices for Incremental Compilation Partitions and Floorplan Assignments - 2015-11-02

Source Name: DITA

1. Best Practices for Incremental Compilation Partitions and Floorplan Assignments
1.1. About Incremental Compilation and Floorplan Assignments
1.2. Incremental Compilation Overview
1.2.1. Recommendations for the Netlist Type
1.3. Design Flows Using Incremental Compilation
1.3.1. Using Standard Flow
1.3.2. Using Team-Based Flow
1.3.2.1. Using Third-Party IP Delivery Flow
1.3.3. Combining Design Flows
1.3.4. Project Management in Team-Based Design Flows
1.3.4.1. Using a Source Control System
1.3.4.2. Using a Copy of the Top-Level Project
1.3.4.3. Using a Separate Project
1.3.4.4. Using Scripts
1.3.4.5. Using Constraints
1.4. Why Plan Partitions and Floorplan Assignments?
1.4.1. Partition Boundaries and Optimization
1.4.1.1. Merging Partitions
1.4.1.2. Resource Utilization
1.4.1.3. Turning On Supported Cross-Boundary Optimizations
1.5. Guidelines for Incremental Compilation
1.5.1. General Partitioning Guidelines
1.5.1.1. Plan Design Hierarchy and Design Files
1.5.1.2. Using Partitions with Third-Party Synthesis Tools
1.5.1.3. Partition Design by Functionality and Block Size
1.5.1.4. Partition Design by Clock Domain and Timing Criticality
1.5.1.5. Consider What Is Changing
1.5.2. Design Partition Guidelines
1.5.2.1. Register Partition Inputs and Outputs
1.5.2.2. Minimize Cross-Partition-Boundary I/O
1.5.2.3. Examine the Need for Logic Optimization Across Partitions
1.5.2.3.1. Keep Logic in the Same Partition for Optimization and Merging
1.5.2.3.1.1. Example—Combinational Logic Path
1.5.2.3.1.2. Example—Fitter Merging
1.5.2.3.2. Merging PLLs and Transceivers (GXB)
1.5.2.4. Keep Constants in the Same Partition as Logic
1.5.2.4.1. Example—Constants in Merged Partitions
1.5.2.5. Avoid Signals That Drive Multiple Partition I/O or Connect I/O Together
1.5.2.5.1. Example—Single Signal Driving More Than One Port
1.5.2.6. Invert Clocks in Destination Partitions
1.5.2.6.1. Example—Clock Signal Inversion
1.5.2.7. Connect I/O Pin Directly to I/O Register for Packing Across Partition Boundaries
1.5.2.7.1. Example—Output Register in Partition Feeding Multiple Output Pins
1.5.2.7.2. Example 2—Input Register in Partition Fed by an Inverted Input Pin or Output Register in Partition Feeding an Inverted Output Pin
1.5.2.8. Do Not Use Internal Tri-States
1.5.2.9. Include All Tri-State and Enable Logic in the Same Partition
1.5.2.10. Summary of Guidelines Related to Logic Optimization Across Partitions
1.5.3. Consider a Cascaded Reset Structure
1.5.4. Design Partition Guidelines for Third-Party IP Delivery
1.5.4.1. Allocate Logic Resources
1.5.4.2. Allocate Global Routing Signals and Clock Networks if Required
1.5.4.3. Assign Virtual Pins
1.5.4.4. Perform Timing Budgeting if Required
1.5.4.5. Drive Clocks Directly
1.5.4.6. Recreate PLLs for Lower-Level Partitions if Required
1.6. Checking Partition Quality
1.6.1. Incremental Compilation Advisor
1.6.2. Design Partition Planner
1.6.3. Viewing Design Partition Planner and Floorplan Side-by-Side
1.6.4. Partition Statistics Report
1.6.5. Report Partition Timing in the Timing Analyzer
1.6.6. Check if Partition Assignments Impact the Quality of Results
1.7. Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery
1.7.1. Creating an .sdc File with Project-Wide Constraints
1.7.1.1. Example Step 1—Project Lead Produces .sdc with Project-Wide Constraints for Lower-Level Partitions
1.7.2. Creating an .sdc with Partition-Specific Constraints
1.7.2.1. Example Step 2: Partition Designer Creates .sdc with Partition-Specific Constraints
1.7.3. Consolidating the .sdc in the Top-Level Design
1.7.3.1. Example Step 3: Project Lead Performs Final Timing Analysis and Sign-off
1.8. Introduction to Design Floorplans
1.8.1. The Difference between Logical Partitions and Physical Regions
1.8.2. Why Create a Floorplan?
1.8.3. When to Create a Floorplan
1.8.3.1. Early Floorplan
1.8.3.2. Late Floorplan
1.9. Design Floorplan Placement Guidelines
1.9.1. Flow for Creating a Floorplan
1.9.2. Assigning Partitions to LogicLock Regions
1.9.3. How to Size and Place Regions
1.9.4. Modifying Region Size and Origin
1.9.5. I/O Connections
1.9.6. LogicLock Resource Exclusions
1.9.6.1. Creating Floorplan Location Assignments With Tcl Commands—Excluding or Filtering Certain Device Elements (Such as RAM or DSP Blocks)
1.9.7. Creating Non-Rectangular Regions
1.10. Checking Floorplan Quality
1.10.1. Incremental Compilation Advisor
1.10.2. LogicLock Region Resource Estimates
1.10.3. LogicLock Region Properties Statistics Report
1.10.4. Locate the Intel® Quartus® Prime Timing Analyzer Path in the Chip Planner
1.10.5. Inter-Region Connection Bundles
1.10.6. Routing Utilization
1.10.7. Ensure Floorplan Assignments Do Not Significantly Impact Quality of Results
1.11. Recommended Design Flows and Application Examples
1.11.1. Create a Floorplan for Major Design Blocks
1.11.2. Create a Floorplan Assignment for One Design Block with Difficult Timing
1.11.3. Create a Floorplan as the Project Lead in a Team-Based Flow
1.12. Document Revision History

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