HLS IP Gen Release Notes - Release Notes for the HLS IP Gen compiler - 2026-07-14

Version: current
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Source Name: Markdown

Preface
What's New
Known issues and limitations
1. Legacy "Intel" references remain in the product
2. Simulation with no kernel launched
3. <cmath> functions — incorrect results
4. Unsupported <cmath> functions
5. Generic simulation failure / missing device support
6. Red Hat* Enterprise Linux* — libnsl library
7. device_global reads
8. Assert macros and text strings
9. Memory system layout and [[intel::fpga_memory("BLOCK_RAM")]]
10. switch vs if for external memories
11. SYCL* limitations
12. Avalon® MM host address bus width (ring interconnect)
13. Multithreading, pipes, and streaming testbenches
14. Lambda kernel names in the optimization report
15. ap_float and -fp-model=fast
16. Agilex 7 and LSU read ports
17. PC-relative offset overflow (large simulations)
18. ap_float ihc_log on Agilex3
19. Simulation of pipelined kernels with II=1
20. device_global of struct with array member
21. Streaming kernel with bool arguments
22. Precision for ap_float_math.hpp exponential functions
23. Native float32 loop-carried accumulation with explicit ii=1 on Agilex devices
24. Stall-free streaming host pipes generate extra ports on the device image boundary
25. Simulation fails when using -fsycl-device-code-split with host pipes
26. Stallable CSR output pipe consecutive write
27. CSR pipes behave differently in emulation and simulation/hardware
Changes in usage
1. sycl::ext::altera::experimental::pipe
Document revision history

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