1. FPGA AI Suite Handbook - 2026-08-18

FPGA AI Suite Handbook
Version
2026.1.1
Product Type
Device Families > Agilex Families > Agilex 5
Device Families > Agilex Families > Agilex 5 > E-Series
Development Software and Tools > AI Development Tools > FPGA AI Suite
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7
Device Families > Agilex Families > Agilex 3
Device Families > Stratix Families
Device Families > Agilex Families > Agilex 7 > I-Series
Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 GX
Device Families > Cyclone Families > Cyclone 10
Device Families > Agilex Families > Agilex 5 > D-Series
Device Families > Agilex Families > Agilex 7 > M-Series
Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
Device Families > Arria Families > Arria 10
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Stratix Families > Stratix 10
Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software
Device Families > Cyclone Families
Device Families > Arria Families
Device Families > Agilex Families > Agilex 3 > C-Series
Resource Type
Documentation > User Guides
ft:sourceName
DITA

The FPGA AI Suite is a suite of tools and design examples to help you get AI inference from your pretrained models running on Altera® FPGA devices, either in concert with a CPU or in a hostless configuration.

The FPGA AI Suite Handbook provides the following information:

  • An overview of the FPGA AI Suite and its components such as the FPGA AI Suite IPs and the FPGA AI Suite compiler.
  • Installation instructions and a list of prerequisites
  • Tutorials and walkthroughs that take you through the process of running inference, including performance and area estimation
  • How to customize your FPGA AI Suite IPs by changing parameters settings.
  • A description of the FPGA AI Suite Compiler and its use modes.
  • Details about the compiler command options and the format of compile inputs and outputs.
  • How to generate RTL and a Quartus® Prime Platform Designer IP index (.ipx) file with the FPGA AI Suite IP generation utility so that you can integrate your FPGA AI Suite IPs with a larger FPGA design.

  • A description of the design and implementation of design examples that you can use to accelerate AI inference using the FPGA AI Suite, Intel® Distribution of OpenVINO™ toolkit, and various development boards (depending on the design example).

Intel® Distribution of OpenVINO™ toolkit Requirement

To use the FPGA AI Suite, you must be familiar with the Intel® Distribution of OpenVINO™ toolkit.

FPGA AI Suite Version 2026.1.1 requires the Intel® Distribution of OpenVINO™ toolkit Version 2025.4. For OpenVINO™ documentation, refer to https://docs.openvino.ai/2025/documentation.html.