AN 1014: Implementing Analog-to-Digital Converter Multilink Design with Agilex™ 7 FPGA F-Tile JESD204C RX IP - Provides guidelines to scale up the single link of the F-Tile JESD204C RX IP design example generated from the Quartus Prime software to handle a dual link system. - 2025-11-24
- Product Type
- Device Families > Agilex Families
- Device Families > Agilex Families > Agilex 7 > F-Series
- Device Families > Agilex Families > Agilex 7
- Resource Type
- Documentation > Application Notes
- Source Name
- DITA