GTS Ethernet Hard IP User Guide - This user guide introduces the GTS Ethernet Hard IP for Agilex® 3 FPGAs and SoCs, emphasizing its features. It then explains the IP parameters and configurations for different supporting modes, and concludes with a detailed functional description. - 2026-08-10
Version
26.1.1
Product Type
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 3
Device Families > Agilex Families > Agilex 3 > C-Series
Resource Type
Documentation > User Guides
Source Name
DITA
1. Overview
1.1. Release Information
1.2. High-Level Functional Overview
1.3. Acronyms
1.4. Agilex® 3 Ethernet Portfolio and Target Applications
1.5. Agilex® 3 Ethernet Hard IP Features
1.5.1. Device Family Support
1.5.2. Device Speed Grade Support
1.5.3. Resource Utilization
1.5.4. Round-Trip Latency
1.6. GTS Ethernet Hard IP Design Flow
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
3.1. Create Quartus Project
3.2. Configure GTS Ethernet Hard IP
3.3. Generate HDL for Synthesis and Simulation
3.4. Generated File Structure
3.5. Generate GTS EHIP Design Example
3.5.1. Directory Structure
3.6. Analog Parameter Options
4. Integrate GTS Ethernet Hard IP into Your Application
4.1. Implement Required Clocking
4.1.1. Implement MAC Synchronous Clock Connections
4.1.2. Implement Clock Connections to MAC Asynchronous Operation
4.1.3. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.4. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets
4.2.1. Reset Sequence
4.2.2. Connect the GTS Reset Sequencer IP
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer IP
4.3. Connect the Status Interface
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface
4.4.3.1. Connect the TX MAC Flow Control Interface
4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface
4.5.1. Connect the MII PCS Mode TX Interface
4.5.2. Connect the MII PCS Mode RX Interface
4.6. Connect the PCS66 Client Interface – FlexE and EoOTN
4.6.1. Connect the FlexE and EoOTN Mode TX Interface
4.6.2. Connect the FlexE and EoOTN Mode RX Interface
4.7. Connect the Precision Time Protocol Interface
4.7.1. Connect the Time-of-Day Interface
4.7.2. Connect the TX Two-Step Timestamp Interface
4.7.3. Connect the TX One-Step Timestamp Interface
4.7.3.1. PTP Field Offset for 1-Step Operation
4.7.4. Connect the RX Timestamp Interface
4.7.5. Connect the PTP Status Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.11.1. Port Mapping from Ethernet IP (Dynamically Reconfigurable Mode) to HSSI Support Logic Generation (DR Top)
5. Simulate and Compile (MAC+PCS) Design Example
5.1. Design Example Features
5.2. Design Example Components
5.3. Simulate the Design Example
5.3.1. Simulation Testbench Flow
5.3.2. Verify the Simulation Results
5.4. Compile the Design Example
6. Simulate and Compile (MII PCS Only/PCS66 EoOTN/PCS66 FlexE) Design Example
6.1. Design Example Features
6.2. Design Example Components
6.3. Simulate the Design Example
6.3.1. Simulation Testbench Flow
6.3.2. Simulators Output
6.4. Compile the Design Example
7. Simulate and Compile SyncE Design Example
7.1. Design Example Features
7.2. Design Example Components
7.3. Simulate the Design Example
7.3.1. Simulation Testbench Flow 10GE Ethernet with SyncE
7.3.2. Simulator Output
7.4. Compile the Design Example
8. Simulate and Compile PTP1588 Design Example
8.1. Design Example Features
8.2. Design Example Components
8.3. Simulate the Design Example
8.3.1. Simulation Testbench Flow
8.3.2. Simulator Output
8.4. Compile the Design Example
9. Simulate and Compile (Dynamically Reconfigurable Mode)
9.1. Design Example Features
9.2. Design Example Components
9.3. Simulate the Design Example
9.3.1. Simulation Testbench Flow
9.3.2. Verify the Simulation Results
9.4. Compile the Design Example
10. Simulate, and Compile (Dynamically Reconfigurable Mode with PTP1588)
10.1. Design Example Features
10.2. Design Example Components
10.3. Simulate the Design Example
10.3.1. Simulation Testbench Flow
10.3.2. Verify the Simulation Results
10.4. Compile the Design Example
11. Simulate, and Compile (Dynamically Reconfigurable Mode) - MII PCS Only/PCS66 EoOTN/PCS66 FlexE
11.1. Design Example Features
11.2. Design Example Components
11.3. Simulate the Design Example
11.3.1. Simulation Testbench Flow
11.3.2. Verify the Simulation Results
11.4. Compile the Design Example
12. Simulate and Compile - Auto-Negotiation and Link Training
12.1. Auto-Negotiation and Link Training for General Ethernet Mode
12.2. Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT
12.3. Design Example Features
12.4. Design Example Components
12.5. Simulate the Design Example
12.5.1. Simulation Testbench Flow
12.5.2. Simulation Output
12.6. Compile the Design Example
13. Troubleshoot and Diagnose Issues
13.1. Enable Diagnostic Lookback Modes
13.1.1. Internal Serial Loopback
13.1.2. Enable MAC Loopback
13.1.3. Enable PCS Loopback
13.1.4. Enable External Loopback
13.1.5. Packet Client Loopback
13.2. Troubleshoot the Reset Sequence
13.2.1. Debug the Power Up Reset Sequence
13.2.2. Debug the TX Reset Entry Sequence
13.2.3. Debug the TX Reset Exit Sequence
13.2.4. Debug the RX Reset Entry Sequence
13.2.5. Debug the RX Reset Exit Sequence
13.2.6. Debug the Auto Recovery Reset Sequence
14. Appendix A: Functional Description
14.1. Datapath Description
14.2. GTS Ethernet Hard IP MAC
14.2.1. MAC TX Datapath
14.2.1.1. Insert TX Preamble, Start, and SFD
14.2.1.2. Insert Source Address
14.2.1.3. Process Length/Type Field
14.2.1.4. Pad the Client Frame
14.2.1.5. Insert Frame Check Sequence (CRC-32)
14.2.1.6. Generate and Insert Inter-Packet Gap
14.2.2. MAC RX Datapath
14.2.2.1. Process RX Preamble
14.2.2.2. Check RX Strict SFD
14.2.2.3. Check RX FCS
14.2.2.4. Handle RX Malformed Packet
14.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames
14.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors
14.2.2.7. Inter-Packet Gap
14.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC)
14.2.3.1. Conditions Triggering XOFF Frame Transmission
14.2.3.2. Conditions Triggering XON Frame Transmission
14.2.3.3. Pause Control and Generation Interface
14.2.3.4. Pause Control Frame Filtering
14.2.4. Link Fault Signaling
14.2.5. Order of Ethernet Transmission:
14.3. PCS, EoOTN, and FlexE Modes
14.3.1. PCS Mode
14.3.2. EoOTN Mode
14.3.3. FlexE Mode
14.4. Precision Time Protocol Interface
14.4.1. Features
14.4.2. PTP User Flow
14.4.2.1. PTP TX User Flow
14.4.2.2. PTP RX User Flow
14.4.3. Make PTP UI Adjustments
14.4.3.1. Adjust TX UI
14.4.3.2. Adjust RX UI
14.4.4. Reference Time Interval
14.5. Auto-Negotiation and Link Training
14.5.1. Switching between Copper cable (DAC) and Optical cable (AOC)
14.5.1.1. Sequence to switch from DAC to AOC
14.5.1.2. Sequence to switch back from AOC to DAC
14.5.2. Resetting the AN/LT Controller
15. Appendix B: Configuration Registers
15.1. Ethernet Avalon® Memory-Mapped Interface Address Space
15.2. Packet Client Registers
16. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex® 3 FPGAs and SoCs