GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs - The GTS Transceiver PHY User Guide describes the architecture and implementation details for the Agilex® 3 FPGA GTS transceivers, GTS PMA/FEC Direct PHY Intel® FPGA IP, GTS System PLL Clocks Intel® FPGA IP, and GTS Reset Sequencer Intel® FPGA IP. Refer to these chapters for IP instantiation, connection, simulation, and placement for Agilex® 3 FPGA GTS transceiver designs. - 2025-04-05

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25.1