GTS Transceiver PHY User Guide Agilex™ 3 FPGAs and SoCs - The GTS Transceiver PHY User Guide describes the architecture and implementation details for the Agilex 3 FPGA GTS transceivers, GTS PMA/FEC Direct PHY IP, GTS System PLL Clocks IP, and GTS Reset Sequencer IP. Refer to these chapters for IP instantiation, connection, simulation, and placement for Agilex 3 FPGA GTS transceiver designs. - 2025-08-04

Version

25.1.1

Product Type

Device Families > Agilex Families

Device Families > Agilex Families > Agilex 3

Device Families > Agilex Families > Agilex 3 > C-Series

Resource Type

Documentation > User Guides

Source Name

DITA