Clocking and PLL User Guide Agilex™ 3 FPGAs and SoCs - Describes the Agilex 3 device programmable clock routing network and I/O PLLs for clock management and synthesis. Includes information about the Clock Control Altera FPGA IP and IOPLL FPGA IP . - 2026-01-26

Version

25.1.1

Product Type

Device Families > Agilex Families

Device Families > Agilex Families > Agilex 3

Device Families > Agilex Families > Agilex 3 > C-Series

Resource Type

Documentation > User Guides

Source Name

DITA