GTS JESD204B IP User Guide - Describes the features of the GTS JESD204B and provides instructions and guidelines about how to configure and run the IP. - 2025-10-31

Version: 25.3

1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B IP
2.1. Release Information
2.2. Device Family Support
2.3. Datapath Modes
2.4. IP Variation
2.5. GTS JESD204B IP Configuration
Channel Bonding
2.7. Performance and Resource Utilization
3. Getting Started
3.1. Introduction to IP Cores
3.2. Installing and Licensing IP Cores
3.3. Altera FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.6.1. Creating a New Quartus Prime Project
3.6.2. Parameterizing and Generating the IP
3.6.3. Compiling the GTS JESD204B IP Core Design
3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations
3.7.1. Integrating the GTS JESD204B IP in Platform Designer
3.7.2. Pin Assignments
Configuring the GTS Reset Sequencer IP
REFCLK Recovery (CLK RX)
GTS JESD204B IP Parameters
3.9. Analog Parameter Settings
3.10. GTS JESD204B IP Component Files
4. GTS JESD204B IP Functional Description
4.1. Transmitter
4.1.1. TX Data Link Layer
4.1.1.1. TX CGS
4.1.1.2. TX ILAS
4.1.1.3. User Data Phase
4.1.2. TX PHY Layer
4.2. Receiver
4.2.1. RX Data Link Layer
4.2.1.1. RX CGS
4.2.1.2. Frame Synchronization
4.2.1.3. Frame Alignment
4.2.1.4. Lane Alignment
4.2.1.5. ILAS Data
4.2.1.6. Initial Lane Synchronization
4.2.2. RX PHY Layer
4.3. Dual Simplex Support
4.4. Operation
4.4.1. Operating Modes
4.4.1.1. Subclass 0 Operating Mode
4.4.1.2. Subclass 1 Operating Mode
4.4.1.3. Subclass 2 Operating Mode
4.4.2. Scrambler/Descrambler
4.4.3. SYNC_N Signal
4.4.4. Link Reinitialization
4.4.5. Link Startup Sequence
4.4.6. Error Reporting Through SYNC_N Signal
4.5. Clocking Scheme
4.5.1. Device Clock
4.5.2. Link Clock
4.5.3. Local MultiFrame Clock
4.5.4. Clock Correlation
4.5.5. GTS Reset Sequencer IP Clock
HVIO PLL Clocking Mode
4.6. Reset Scheme
4.6.1. Reset Sequence
4.6.2. TX Reset Entry and Exit Sequence
4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals
4.7.1. Transmitter Signals
4.7.2. Receiver Signals
4.8. Registers
4.8.1. Register Access Type Convention
4.8.2. Register Map and Definition
4.8.3. Transmitter Registers
4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
5.1. Constraining Incoming SYSREF Signal
5.2. Programmable RBD Offset
5.3. Programmable LMFC Offset
5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines
6.1. Clocking Scheme
6.2. GTS JESD204B Parameters
6.3. SPI Programming
6.4. Converter and FPGA Operating Conditions
6.5. Signal Polarity and FPGA Pin Assignment
6.6. Transceiver Toolkit
7. Document Revision History for the GTS JESD204B User Guide

Back to home page