GTS DisplayPort FPGA IP Design Example User Guide - Describes the DisplayPort IP design example for Agilex 3 C-Series and Agilex 5 E-Series devices. - 2026-05-08

Version: 26.1

1. DisplayPort IP Design Example Quick Start Guide
1.1. Directory Structure
1.2. Hardware and Software Requirements
1.3. Generating the Design
1.4. Simulating the Design
1.5. Compiling and Testing the Design
1.5.1. Compiling and Testing the Design Using Agilex™ 3 FPGA and SoC C-Series Development Kit
1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode
1.5.4. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with Bitec Rev 8 Daughter Card
1.6. Regenerating the Nios V .elf File
1.7. DisplayPort IP Design Example Parameters
2. DisplayPort IP Design Examples
2.1. Design Components
2.2. DisplayPort IP Design Example Clock Domains
2.3. Interface Signals and Parameters
2.4. Simulation Testbench
3. DisplayPort SST Parallel Loopback without PCR Design Example
3.1. Features
3.2. Functional Description
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
4.1. Features
4.2. Functional Description
5. DisplayPort SST TX-Only Design Example
5.1. DisplayPort SST TX-Only Features
5.2. DisplayPort SST TX-Only Functional Description
6. DisplayPort SST RX-Only Design Example
6.1. DisplayPort SST RX-Only Features
6.2. DisplayPort SST RX-Only Functional Description
7. HDCP Over DisplayPort Design Example
7.1. High-bandwidth Digital Content Protection (HDCP)
7.2. HDCP Over DisplayPort Design Example Architecture
7.3. Nios® V Processor Software Flow
7.4. Design Walkthrough
7.4.1. Setting Up the Hardware
7.4.2. Generating the Design
7.4.3. Including HDCP Production Keys
7.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0)
7.4.3.1.1. HDCP Key Mapping from DCP Key Files
7.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files
7.4.3.1.3. hdcp2x_rx_kmem.v file
7.4.3.1.4. hdcp2x_tx_kmem.v file
7.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
7.4.3.2.1. Altera® KEYENC
7.4.3.2.2. Key Programmer
7.4.4. Compiling the Design
7.4.5. Viewing the Results
7.5. Protection of Encryption Key Embedded in FPGA Design
7.5.1. Security Considerations
7.6. Debug Guidelines
7.6.1. HDCP Status Signals
7.6.2. Modifying HDCP Software Parameters
7.6.3. Frequently Asked Questions (FAQ)
8. Document Revision History for the GTS DisplayPort FPGA IP Design Example User Guide

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