GTS HDMI IP User Guide - Describes the features, ports, registers, and parameters of the GTS HDMI IP . - 2026-05-22

Version: 26.1

1. GTS HDMI IP Quick Reference
1.1. Terms and Acronyms
2. About the GTS HDMI IP
2.1. GTS HDMI IP Device Family Support
2.2. GTS HDMI IP Device Feature Support
2.3. GTS HDMI IP Release Information
2.4. GTS HDMI IP Performance and Resource Usage
3. GTS HDMI IP Getting Started
3.1. Installing and Licensing IPs
3.1.1. IP Evaluation Mode
3.2. Specifying IP Parameters and Options
4. GTS HDMI IP Hardware Design Examples
5. HDMI Source
5.1. Source Functional Description
5.1.1. Source Scrambler, TMDS/TERC4 Encoder
5.1.2. Source Video Resampler
5.1.3. Source Window of Opportunity Generator
5.1.4. Source Auxiliary Packet Encoder
5.1.5. Source Auxiliary Packet Generators
5.1.6. Source Auxiliary Data Path Multiplexers
5.1.7. Source Auxiliary Control Port
5.1.7.1. Source General Control Packet (GCP)
5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields
5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields
5.1.8.2. Audio Metadata Bundle Bit-Fields
5.1.9. FRL Packetizer
5.1.10. FRL Character Block and Super Block Mapping
5.1.11. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion
5.1.12. FRL Scrambler and Encoder
5.1.13. Source FRL Resampler
5.1.14. TX Core-PHY Interface
5.1.14.1. TX Oversampler
5.1.14.2. Clock Enable Generator
5.1.15. I2C Controller
5.1.16. Pixel Repetition
5.1.17. AXI4-Stream to Clocked Video Converter (AXI2CV)
5.1.18. AXI4-Stream to Clocked Video Converter (AXI2CV) Remap
5.1.19. Avalon Memory-Mapped Demultiplexer
5.1.20. HDMI TX Register
5.1.21. HDMI TX Interrupt
5.1.22. TX AXI4-Stream Auxiliary Bridge
5.1.23. TX Auxiliary User Packet
5.1.24. TX AXI4-Stream Auxiliary Arbiter
5.1.25. TX AXI4-Stream Auxiliary Packetizer
5.1.26. TX Avalon-ST Auxiliary Arbiter
5.2. Source Interfaces
5.3. Source Clock Tree
5.4. Link Training Procedure
5.5. FRL Clocking Scheme
5.6. Valid Video Data
5.7. Source Deep Color Implementation
5.8. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
6. HDMI Sink
6.1. Sink Functional Description
6.1.1. Sink Word Alignment and Channel Deskew
6.1.2. Sink Descrambler, TMDS/TERC4 Decoder
6.1.3. Sink Auxiliary Decoder
6.1.4. Sink Auxiliary Packet Capture
6.1.5. Sink Video Resampler
6.1.6. Sink Auxiliary Data Port
6.1.6.1. Sink General Control Packet (GCP)
6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields
6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields
6.1.7.2. Audio Metadata Bundle Bit-Fields
6.1.8. Status and Control Data Channel (SCDC) Interface
6.1.9. FRL Depacketizer
6.1.10. Sink FRL Character Block and Super Block Demapper
6.1.11. Sink FRL Descrambler and Decoder
6.1.12. Sink FRL Resampler
6.1.13. RX Core-PHY Interface
6.1.13.1. RX Oversampler
6.1.14. I2C Target
6.1.15. I2C and EDID RAM Blocks
6.1.16. Pixel De-repetition
6.1.17. Clocked Video to AXI4-Stream (CV2AXI) Remap
6.1.18. Clocked Video to AXI4-Stream Converter (CV2AXI)
6.1.19. Avalon Memory-Mapped Demultiplexer
6.1.20. HDMI RX Register
6.1.21. HDMI RX Interrupt
6.1.22. RX AXI4-Stream Auxiliary Bridge
6.1.23. RX Auxiliary Packet Filter
6.1.24. RX Auxiliary User Packetizer
6.1.25. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.2. Sink Interfaces
6.3. Sink Clock Tree
6.4. Link Training Procedure
6.5. Sink Deep Color Implementation
7. Creating Dual Simplex Groups
8. GTS HDMI IP Parameters
8.1. HDMI Source Parameters
8.2. HDMI Sink Parameters
9. HDMI Simulation Example
9.1. Simulation Walkthrough
10. Registers
10.1. HDMI Source Register
10.1.1. HDMI Source Core Register Summary
10.1.1.1. STATUS_CONTROL (0x00)
10.1.1.2. IRQ_STATUS (0x01)
10.1.1.3. IRQ_MASK (0x02)
10.1.1.4. VIDEO_FORMAT (0x03)
10.1.1.5. AVI_CONTROL (0x08)
10.1.1.6. AVI_PACKET_DATA0 (0x09)
10.1.1.7. AVI_PACKET_DATA1 (0x0A)
10.1.1.8. AVI_PACKET_DATA2 (0x0B)
10.1.1.9. AVI_PACKET_DATA3 (0x0C)
10.1.1.10. VSI_CONTROL (0x0D)
10.1.1.11. VSI_PACKET_HEADER (0x0E)
10.1.1.12. VSI_PACKET_DATA0 (0x0F)
10.1.1.13. VSI_PACKET_DATA1 (0x10)
10.1.1.14. USER_PACKET_STATUS_CONTROL (0x12)
10.1.1.15. USER_PACKET_HEADER (0x013)
10.1.1.16. USER_PACKET_DATA0 (0x014)
10.1.1.17. USER_PACKET_DATA1 (0x015)
10.1.1.18. USER_PACKET_DATA2 (0x016)
10.1.1.19. USER_PACKET_DATA3 (0x017)
10.1.1.20. USER_PACKET_DATA4 (0x018)
10.1.1.21. USER_PACKET_DATA5 (0x019)
10.1.1.22. USER_PACKET_DATA6 (0x01A)
10.1.1.23. USER_PACKET_DATA7 (0x01B)
10.1.1.24. AUDIO_INFOFRAME_CONTROL (0x20)
10.1.1.25. AUDIO_INFOFRAME_PACKET_DATA0 (0x21)
10.1.1.26. AUDIO_INFOFRAME_PACKET_DATA1 (0x22)
10.1.1.27. AUDIO_METADATA_CONTROL (0x24)
10.1.1.28. AUDIO_METADATA_PACKET_HEADER (0x025)
10.1.1.29. AUDIO_METADATA_PACKET_DATA0 (0x026)
10.1.1.30. AUDIO_METADATA_PACKET_DATA1 (0x027)
10.1.1.31. AUDIO_METADATA_PACKET_DATA2 (0x028)
10.1.1.32. AUDIO_METADATA_PACKET_DATA3 (0x029)
10.1.1.33. AUDIO_METADATA_PACKET_DATA4 (0x02A)
10.1.1.34. AUDIO_METADATA_PACKET_DATA5 (0x02B)
10.1.1.35. SCDC_FRL_CONTROL (0x031)
10.2. HDMI Source AXI2CV Register
10.2.1. HDMI Source AXI2CV Register Summary
10.2.2. HDMI Source AXI2CV Register Description
10.2.2.1. STATUS (0x50)
10.2.2.2. VIDEO_MODE_MATCH (0x51)
10.2.2.3. VIDEO_MODE_BANK_SELECT (0x53)
10.2.2.4. VIDEO_MODE_CONTROL (0x54)
10.2.2.5. VIDEO_MODE_SAMPLE_COUNT(0x55)
10.2.2.6. VIDEO_MODE_F0_LINE_COUNT (0x56)
10.2.2.7. VIDEO_MODE_F1_LINE_COUNT (0x57)
10.2.2.8. VIDEO_MODE_HORIZONTAL_FRONT_PORCH (0x58)
10.2.2.9. VIDEO_MODE_HORIZONTAL_SYNC_LENGTH (0x59)
10.2.2.10. VIDEO_MODE_HORIZONTAL_BLANKING (0x5A)
10.2.2.11. VIDEO_MODE_VERTICAL_FRONT_PORCH (0x5B)
10.2.2.12. VIDEO_MODE_VERTICAL_SYNC_LENGTH (0x5C)
10.2.2.13. VIDEO_MODE_VERTICAL_BLANKING (0x5D)
10.2.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)
10.2.2.15. VIDEO_MODE_F0_VERTICAL_SYNC_LENGTH (0x5F)
10.2.2.16. VIDEO_MODE_F0_VERTICAL_BLANKING (0x60)
10.2.2.17. VIDEO_MODE_ACTIVE_PICTURE_LINE (0x61)
10.2.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62)
10.2.2.19. VIDEO_MODE_FIELD_RISING (0x63)
10.2.2.20. VIDEO_MODE_FIELD_FALLING (0x64)
10.2.2.21. VIDEO_MODE_HORIZONTAL_SYNC_POLARITY (0x6B)
10.2.2.22. VIDEO_MODE_VERTICAL_SYNC_POLARITY (0x6C)
10.2.2.23. VIDEO_MODE_VALID (0x6D)
10.3. HDMI Sink Register
10.3.1. HDMI Sink Register Summary
10.3.1.1. STATUS (0x01)
10.3.1.2. IRQ_STATUS (0x02)
10.3.1.3. IRQ_MASK (0x03)
10.3.1.4. HOTPLUG (0x04)
10.3.1.5. LINK_MODE (0x05)
10.3.1.6. VIDEO_COLOR (0x06)
10.3.1.7. AVI_PACKET_DATA0 (0x0C)
10.3.1.8. AVI_PACKET_DATA1 (0x0D)
10.3.1.9. AVI_PACKET_DATA2 (0x0E)
10.3.1.10. AVI_PACKET_DATA3 (0x0F)
10.3.1.11. USER_PACKET_FILTER (0x10)
10.3.1.12. USER_BUFFER_STATUS_CONTROL (0x11)
10.3.1.13. USER_BUFFER_LEVEL (0x12)
10.3.1.14. USER_BUFFER_DATA (0x13)
10.3.1.15. AUX_PACKET_FILTER (0x14)
10.3.1.16. AUDIO_INFOFRAME_PACKET_DATA0 (0x21)
10.3.1.17. AUDIO_INFOFRAME _PACKET_DATA1 (0x22)
10.3.1.18. AUDIO_METADATA _PACKET_HEADER (0x25)
10.3.1.19. AUDIO_METADATA _PACKET_DATA0 (0x26)
10.3.1.20. AUDIO_METADATA _PACKET_DATA1 (0x27)
10.3.1.21. AUDIO_METADATA _PACKET_DATA2 (0x28)
10.3.1.22. AUDIO_METADATA _PACKET_DATA3 (0x29)
10.3.1.23. AUDIO_METADATA _PACKET_DATA4 (0x2A)
10.3.1.24. AUDIO_METADATA _PACKET_DATA5 (0x2B)
10.3.1.25. VSI_PACKET_DATA0 (0x2C)
10.3.1.26. VSI_PACKET_DATA1 (0x2D)
10.3.1.27. SCDC_FRL_STATUS (0x2E)
10.3.1.28. SCDC_FRL_CONTROL (0x2F)
10.4. HDMI Sink CV2AXI Register
10.4.1. HDMI Sink CV2AXI Register Summary
10.4.2. HDMI Sink CV2AXI Register Description
10.4.2.1. STATUS (0x50)
10.4.2.2. ACTIVE SAMPLE COUNT (0x52)
10.4.2.3. F0_ACTIVE_LINE_COUNT (0x53)
10.4.2.4. F1_ACTIVE_LINE_COUNT (0x54)
10.4.2.5. TOTAL_SAMPLE_COUNT (0x55)
10.4.2.6. F0_TOTAL_LINE_COUNT (0x56)
10.4.2.7. F1_TOTAL_LINE_COUNT (0x57)
10.4.2.8. COLOR_PATTERN (0x5C)
10.4.2.9. CONTROL (0x64)
11. GTS HDMI IP User Guide Archives
12. Document Revision History for the GTS HDMI IP User Guide

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