PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide - This design guidelines user guide provides board implementation recommendations for Agilex™ 5 devices and provides the recommendations for Variable Pitch BGA package variant in High-speed Signal Integrity (HSSI), External Memory Interface (EMIF), Mobile Industry Processor Interface (MIPI), True Differential I/O Interface, and Power Distribution Network (PDN). - 2026-06-12
Product Type
Device Families > Agilex Families > Agilex 5
Device Families > Agilex Families > Agilex 5 > D-Series
Device Families > Agilex Families > Agilex 5 > E-Series
Device Families > Agilex Families
Resource Type
Documentation > User Guides
Source Name
DITA
1. Overview
1.1. Agilex™ 5 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern
2.1. Metal-Defined Board Pad
2.2. Spoked Pad
2.3. Wide Trace Metal-Defined Pad
2.4. Solder Mask-Defined Pad
2.5. Recommended Land Patterns
3. General PCB Design Considerations
3.1. Impedance Tolerances
3.2. Reference Planes
3.3. Layer Assignment
3.4. Via Drill Size
3.5. Fiber Weave
3.6. PCB Traces
3.6.1. Zig-Zag Routing
3.6.2. Image Rotation
3.7. PCB Vias
3.8. AC Coupling Capacitors
3.9. Other Considerations
4. VPBGA PCB Routing Guidelines
4.1. Pin Distribution and Ball Pitches
4.2. Fan-Out and Routing Strategy
4.3. Power Pins
4.4. HSSI Reference PCB Stack-up
4.5. Agilex™ 5 GTS Transceiver
4.5.1. HSSI Pin-Field Breakout for VPBGA
4.6. GTS Transceiver PCIe® 4.0 16 GT/s NRZ Interface Design Guidelines
4.6.1. GTS Transceiver Channel Recommendations
4.6.2. General Guidelines for GTS Transceiver PCIe® Gen 4.0 Interface
4.6.3. PCIe® Add-In Card Edge Finger
4.7. GTS Transceiver Ethernet 25G NRZ Interface Design Guidelines
4.7.1. GTS Transceiver Channel Recommendations
4.7.2. General Guidelines for GTS Transceiver Ethernet Interface
4.7.3. Quad Small Form-factor Pluggable Connector Routing
4.7.4. Small Form-factor Pluggable (SFP) Connector Routing
4.7.5. Other Connectors
4.7.5.1. ADM/F Connectors
4.7.5.2. DP and HDMI Connectors
4.7.5.3. FMC+ Connectors
5. MBGA PCB Routing Guidelines
5.1. Typical Design Rules for Type-IV HDI in a 0.5 mm MBGA
5.2. HSSI Breakout
5.3. EMIF Breakout
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
6.1. General DDR Signal Routing Guideline on PCB
6.1.1. FPGA DDR Break Out Routing
6.1.2. DRAM Break Out in Layout Routing
6.1.3. Ground Plane and Return Path
6.2. General Notes for EMIF Routing Guidelines Table
6.3. EMIF Board Layout Guideline for Agilex™ 5 E-Series Group B Device
6.3.1. LPDDR5 Interface Design Guidelines
6.3.1.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.3.2. LPDDR4 Interface Design Guidelines
6.3.2.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface)
6.3.2.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.3.3. DDR4 Interface Design Guidelines
6.3.3.1. Single Rank ×8 Memory Down Topology
6.3.3.2. Single Rank ×16 Memory Down Topology
6.3.3.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies
6.3.3.4. Skew Matching Guidelines for DDR4 Memory Down Configurations
6.3.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations
6.4. EMIF Board Layout Guideline for Agilex™ 5 E-Series Group A Device
6.4.1. LPDDR5 Interface Design Guidelines
6.4.1.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.4.2. LPDDR4 Interface Design Guidelines
6.4.2.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface)
6.4.2.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.4.3. DDR5 Interface Design Guidelines
6.4.3.1. DDR5 Discrete Component/Memory Down Topology : Single Rank x8/x16 or Dual Rank x8/x16
6.4.3.2. Tables for Comprehensive Routing Guidelines for Each DDR5 Signal
6.4.3.3. CA_ODT Connection Guidelines in DDR5 Component Down Fly-By Topology
6.4.4. DDR4 Interface Design Guidelines
6.4.4.1. Single Rank ×8 Memory Down Topology
6.4.4.2. Single Rank ×16 Memory Down Topology
6.4.4.3. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies
6.4.4.4. Skew Matching Guidelines for DDR4 Memory Down Configurations
6.4.4.5. Power Delivery Recommendation for DDR4 Discrete Configurations
6.5. EMIF Board Layout Guideline for Agilex™ 5 D-Series Device
6.5.1. LPDDR5 Interface Design Guidelines
6.5.1.1. LPDDR5 Memory Down Topology (Single Rank or Dual-Rank)
6.5.2. LPDDR4 Interface Design Guidelines
6.5.2.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface)
6.5.2.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
6.5.3. DDR5 Interface Design Guidelines
6.5.3.1. DDR5 Discrete Component/Memory Down Topology : Single Rank x8/x16 or Dual Rank x8/x16
6.5.3.2. Tables for Comprehensive Routing Guidelines for Each DDR5 Signal
6.5.3.3. CA_ODT Connection Guidelines in DDR5 Component Down Fly-By Topology
6.5.3.4. DDR5 RDIMM, UDIMM and SODIMM Topology
6.5.3.5. Tables for Comprehensive Routing Guidelines for DDR5 UDIMM, RDIMM and SODIMM, 1 DIMM per Channel
6.5.3.6. DDR5 RDIMM Power Management IC
6.6. DDR4 Interface Design Guidelines
6.6.1. DDR4 Routing Guidelines DDR4 Discrete/Memory Down Topology
6.6.2. Single Rank ×8 Memory Down Topology
6.6.3. Single Rank ×16 Memory Down Topology
6.6.4. VREF_CA/RESET Signal Routing Guidelines for Memory Down Topologies
6.6.5. Skew Matching Guidelines for DDR4 Memory Down Configurations
6.6.6. Power Delivery Recommendation for DDR4 Memory Down Configurations
6.6.7. DDR4 Routing Guidelines for Various DDR4 DIMM Topologies
6.6.7.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM and SODIMM DDR4 Topologies
6.6.7.2. Skew Matching Guidelines for DIMM Configurations
6.6.7.3. Power Delivery Recommendations for the Memory/DIMM Sides
6.7. LPDDR5, LPDDR4, DDR5 and DDR4 Simulation Strategy
6.7.1. EMIF Eye Mask Margin Guideline
6.7.1.1. Simulating Agilex™ 5 Device Transmission to DDR4/LPDDR4 or DDR5/LPDDR5 Receiver
6.7.1.2. Simulating DDR4/LPDDR4 or DDR5/LPDDR5 Interface Transmission to Agilex™ 5 Device
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines (VPBGA and MBGA)
9. HVIO Interface PCB Routing Guidelines (VPBGA and MBGA)
10. Power Distribution Network Design Guidelines
10.1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
10.1.1. Device Guidelines Status for Agilex™ 5 Devices
10.2. Power Delivery Overview
10.2.1. Power Architecture
10.2.1.1. Power Budget
10.2.1.2. Power Tree
10.2.1.2.1. Recommended Power Tree for SmartVID Devices with GTS Transceiver
10.2.1.2.2. Recommended Power Tree for Non-SmartVID Devices with GTS Transceiver
10.2.2. Rail Merger Requirements
10.2.3. Power Rails Specification
10.2.3.1. Power Nets
10.2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
10.2.3.2. Power Rails Tolerance
10.2.3.3. Power Nets and Transient Specifications
10.2.4. Decoupling Capacitors Recommendation
10.2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary
10.2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
10.3. Board Power Delivery Network Recommendations
10.3.1. Board Decoupling Capacitors Guide
10.3.2. FPGA Core Fabric VCC Voltage Regulator Selection
10.3.3. Remote Sense Connections
10.3.4. Load Line Requirements
10.3.5. VCC Core Board Current Slew Rate
10.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
10.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
10.5. PCB PDN Design Guideline for Unused GTS Transceiver
10.5.1. PDN Design Guideline for Unused GTS Transceiver
10.6. PCB Voltage Regulator Recommendation for PCB Power Rails
10.7. Board PDN Simulations
10.8. Agilex™ 5 Device Family PDN Design Summary
11. Document Revision History for the PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide: Agilex™ 5 FPGAs and SoCs