GTS EthernetHard IP User Guide - This user guide commences with an introduction to GTS Ethernet Hard IP and its features, followed by an explanation of IP parameters and configurations for various IP supporting modes. This user guide concludes with a functional description of GTS Ethernet Hard IP . - 2026-04-13
Version
25.3.1
Product Type
Device Families > Agilex Families > Agilex 5
Device Families > Agilex Families > Agilex 5 > E-Series
Device Families > Agilex Families
Resource Type
Documentation > User Guides
Source Name
DITA
1. Overview
1.1. Release Information
1.2. High-Level Functional Overview
1.3. Acronyms
1.4. Agilex® 5 Ethernet Portfolio and Target Applications
1.5. Agilex® 5 Ethernet Hard IP Features
1.5.1. Device Family Support
1.5.2. Device Speed Grade Support
1.5.3. Resource Utilization
1.5.4. Round-Trip Latency
1.6. GTS Ethernet Hard IP Design Flow
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
3.1. Create Quartus Project
3.2. Configure GTS Ethernet Hard IP
3.3. Generate HDL for Synthesis and Simulation
3.4. Generated File Structure
3.5. Generate GTS EHIP Design Example
3.5.1. Directory Structure
3.6. Analog Parameter Options
4. Integrate GTS Ethernet Hard IP into Your Application
4.1. Implement Required Clocking
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets
4.2.1. Reset Sequence
4.2.2. Connect the GTS Reset Sequencer IP
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer IP
4.3. Connect the Status Interface
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface
4.4.3.1. Connect the TX MAC Flow Control Interface
4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface
4.5.1. Connect the MII PCS Mode TX Interface
4.5.1.1. Insert Alignment Marker
4.5.2. Connect the MII PCS Mode RX Interface
4.5.2.1. Receive Alignment Marker
4.6. Connect the PCS66 Client Interface – FlexE and EoOTN
4.6.1. Connect the FlexE and EoOTN Mode TX Interface
4.6.1.1. Insert Alignment Marker
4.6.2. Connect the FlexE and EoOTN Mode RX Interface
4.6.2.1. Receive Alignment Marker
4.7. Connect the Precision Time Protocol Interface
4.7.1. Connect the Time-of-Day Interface
4.7.2. Connect the TX Two-Step Timestamp Interface
4.7.3. Connect the TX One-Step Timestamp Interface
4.7.3.1. PTP Field Offset for 1-Step Operation
4.7.4. Connect the RX Timestamp Interface
4.7.5. Connect the PTP Status Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.11.1. Port Mapping from Ethernet IP (Dynamically Reconfigurable Mode) to HSSI Support Logic Generation (DR Top)
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
5.1. Design Example Features
5.2. Design Example Components
5.3. Simulate the Design Example
5.3.1. Simulation Testbench Flow
5.3.2. Verify the Simulation Results
5.4. Compile the Design Example
5.5. Validate the Design Example
5.5.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
5.5.3. Run the Hardware Test
6. Simulate, Compile, and Validate (MII PCS Only/PCS66 EoOTN/PCS66 FlexE) - Single Instance
6.1. Design Example Features
6.2. Design Example Components
6.3. Simulate the Design Example
6.3.1. Simulation Testbench Flow
6.3.2. Simulators Output
5.4. Compile the Design Example
5.5. Validate the Design Example
5.5.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
6.5.3. Run the Hardware Test
7. Simulate, Compile, and Validate SyncE - Single Instance
7.1. Design Example Features
7.2. Design Example Components
7.3. Simulate the Design Example
7.3.1. Simulation Testbench Flow for Single Instance with SyncE
7.3.2. Simulator Output
5.4. Compile the Design Example
5.5. Validate the Design Example
5.5.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
5.5.3. Run the Hardware Test
8. Simulate and Compile PTP1588 - Single Instance
8.1. Design Example Features
8.2. Design Example Components
8.3. Simulate the Design Example
8.3.1. Simulation Testbench Flow
8.3.2. Simulator Output
5.4. Compile the Design Example
5.5. Validate the Design Example
5.5.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
8.5.3. Run the Hardware Test
9. Simulate, Compile, and Validate - Multiple Instance
9.1. Design Example Features
9.2. Design Example Components
9.3. Simulate the Design Example
9.3.1. Simulation Testbench Flow for MAC Mode
9.3.2. Simulator Output
5.4. Compile the Design Example
5.5. Validate the Design Example
5.5.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
9.5.3. Run the Hardware Test
10. Simulate, Compile, and Validate (Dynamically Reconfigurable Mode - MAC + PCS)
10.1. Design Example Features
10.2. Design Example Components
10.3. Simulate the Design Example
10.3.1. Simulation Testbench Flow
10.3.2. Verify the Simulation Results
5.4. Compile the Design Example
5.5. Validate the Design Example
5.5.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
10.5.3. Run the Hardware Test
11. Simulate, Compile, and Validate (Dynamically Reconfigurable Mode with PTP1588)
11.1. Design Example Features
11.2. Design Example Components
11.3. Simulate the Design Example
11.3.1. Simulation Testbench Flow
11.3.2. Verify the Simulation Results
11.4. Compile the Design Example
11.5. Validate the Design Example
11.5.1. Configure the Clocks in Hardware
11.5.2. Program the FPGA
11.5.3. Run the Hardware Test
12. Simulate, Compile, and Validate (Dynamically Reconfigurable Mode) - MII PCS Only/PCS66 EoOTN/PCS66 FlexE
12.1. Design Example Features
12.2. Design Example Components
12.3. Simulate the Design Example
12.3.1. Simulation Testbench Flow
12.3.2. Verify the Simulation Results
12.4. Compile the Design Example
12.5. Validate the Design Example
12.5.1. Configure the Clocks in Hardware
12.5.2. Program the FPGA
12.5.3. Run the Hardware Test
13. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
13.1. Auto-Negotiation and Link Training for General Ethernet Mode
13.2. Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT
13.3. Design Example Features
13.4. Design Example Components
13.5. Simulate the Design Example
13.5.1. Simulation Testbench Flow
13.5.2. Simulation Output
13.6. Compile the Design Example
13.7. Validate the Design Example
13.7.1. Configure the Clocks in Hardware
5.5.2. Program the FPGA
13.7.3. Run the Hardware Test
14. Troubleshoot and Diagnose Issues
14.1. Enable Diagnostic Lookback Modes
14.1.1. Internal Serial Loopback
14.1.2. Enable MAC Loopback
14.1.3. Enable PCS Loopback
14.1.4. Enable External Loopback
14.1.5. Packet Client Loopback
14.2. Troubleshoot the Reset Sequence
14.2.1. Debug the Power Up Reset Sequence
14.2.2. Debug the TX Reset Entry Sequence
14.2.3. Debug the TX Reset Exit Sequence
14.2.4. Debug the RX Reset Entry Sequence
14.2.5. Debug the RX Reset Exit Sequence
14.2.6. Debug the Auto Recovery Reset Sequence
14.3. Use Signal Tap Analyzer for Troubleshooting
15. Appendix A: Functional Description
15.1. Datapath Description
15.2. GTS Ethernet Hard IP MAC
15.2.1. MAC TX Datapath
15.2.1.1. Insert TX Preamble, Start, and SFD
15.2.1.2. Insert Source Address
15.2.1.3. Process Length/Type Field
15.2.1.4. Pad the Client Frame
15.2.1.5. Insert Frame Check Sequence (CRC-32)
15.2.1.6. Generate and Insert Inter-Packet Gap
15.2.2. MAC RX Datapath
15.2.2.1. Process RX Preamble
15.2.2.2. Check RX Strict SFD
15.2.2.3. Check RX FCS
15.2.2.4. Handle RX Malformed Packet
15.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames
15.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors
15.2.2.7. Inter-Packet Gap
15.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC)
15.2.3.1. Conditions Triggering XOFF Frame Transmission
15.2.3.2. Conditions Triggering XON Frame Transmission
15.2.3.3. Pause Control and Generation Interface
15.2.3.4. Pause Control Frame Filtering
15.2.4. Link Fault Signaling
15.2.5. Order of Ethernet Transmission:
15.3. PCS, EoOTN, and FlexE Modes
15.3.1. PCS Mode
15.3.2. EoOTN Mode
15.3.3. FlexE Mode
15.4. Precision Time Protocol Interface
15.4.1. Features
15.4.2. PTP User Flow
15.4.2.1. PTP TX User Flow
15.4.2.2. PTP RX User Flow
15.4.3. Make PTP UI Adjustments
15.4.3.1. Adjust TX UI
15.4.3.2. Adjust RX UI
15.4.4. Reference Time Interval
15.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
15.5. Auto-Negotiation and Link Training
15.5.1. Switching between Copper cable (DAC) and Optical cable (AOC)
15.5.1.1. Sequence to switch from DAC to AOC
15.5.1.2. Sequence to switch back from AOC to DAC
15.5.2. Resetting the AN/LT Controller
16. Appendix B: Configuration Registers
16.1. Ethernet Avalon® Memory-Mapped Interface Address Space
16.2. Packet Client Registers
17. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex™ 5 FPGAs and SoCs