GTS Transceiver PHY User Guide Agilex™ 5 FPGAs and SoCs - The GTS Transceiver PHY User Guide describes the architecture and implementation details for the Agilex 5 FPGA GTS transceivers, GTS PMA/FEC Direct PHY IP , GTS System PLL Clocks IP , and GTS Reset Sequencer IP . Refer to these chapters for IP instantiation, connection, simulation, and placement for Agilex 5 FPGA GTS transceiver designs. - 2025-10-17

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25.3