MIPI D-PHY IP Release Notes: Agilex™ 5 FPGAs - The GTS Transceiver PHY User Guide describes the architecture and implementation details for the Agilex™ 5 FPGA GTS transceivers, GTS PMA/FEC Direct PHY Intel® FPGA IP, GTS System PLL Clocks Intel® FPGA IP, and GTS Reset Sequencer Intel® FPGA IP. Refer to these chapters for IP instantiation, connection, simulation, and placement for Agilex™ 5 FPGA GTS transceiver designs. - 2024-04-03

Version

24.1-2.2.0