Power Distribution Network Design Guidelines Agilex™ 5 FPGAs and SoCs - Provides information for the Agilex 5 device family power distribution network (PDN) design guidelines. - 2024-11-21

1. Power Distribution Network Design Guidelines
1.1. Device Guidelines Status for Agilex™ 5 Devices
2. Power Delivery Overview
2.1. Power Architecture
2.1.1. Power Budget
2.1.2. Power Tree
2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages
2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
2.2. Rail Merger Requirements
2.3. Power Rails Specification
2.3.1. Power Nets
2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
2.3.2. Power Rails Tolerance
2.3.3. Power Nets and Transient Specifications
2.4. Decoupling Capacitors Recommendation
2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary
2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations
3.1. Board Decoupling Capacitors Guide
3.2. FPGA Core Fabric VCC Voltage Regulator Selection
3.3. Remote Sense Connections
3.4. Load Line Requirements
3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused GTS Transceiver
5.1. PDN Design Guideline for Unused GTS Transceiver
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 5 Device Family PDN Design Summary
9. Document Revision History for the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs

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