GTS JESD204C IP User Guide - Provides the features, functionality, and guidelines to design the GTS JESD204C IP in Agilex 5 E-Series/D-Series devices. - 2025-12-09

Version: 25.3

1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
2.1. Release Information
2.2. Device Family Support
2.3. GTS JESD204C IP Features
2.4. Performance and Resource Utilization
3. Functional Description
3.1. Clocks
3.1.1. Device Clock
3.1.2. Frame Clock and Link Clock
3.1.3. GTS Reset Sequencer IP Clock
3.2. Local Extended Multiblock Clock
3.2.1. LEMC Counter
3.3. CRC Encoding/Decoding
3.4. Scrambler/Descrambler
4. Getting Started
4.1. Installing and Licensing IP Cores
4.2. Altera FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. GTS JESD204C IP Component Files
4.5. Creating a New Quartus Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the GTS JESD204C IP Design
4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C IP
5.1. Configuring the GTS Reset Sequencer IP
5.2. HVIO PLL Clocking Mode
5.3. Reset Initialization
5.3.1. GTS JESD204C TX Reset Sequence
5.3.2. GTS JESD204C RX Reset Sequence
5.4. Data Mapping Operation
5.5. Configuration Phase
5.6. Link Reinitialization
5.7. SYSREF Sampling
5.8. Interrupt and Error Handling
5.8.1. Interrupt Configuration for TX and RX
5.8.2. Interrupt Top Half ISR Handler
5.8.3. Interrupt Bottom Half ISR Handler
5.9. Multi-Device Synchronization
5.9.1. Multi-Device DAC Application for Subclass 1
5.9.2. Multi-Device ADC Application for Subclass 1
5.10. Deterministic Latency
5.10.1. RBD Tuning Mechanism
5.11. Pin Assignments
5.12. Dual Simplex Support
5.13. Analog Parameter Settings
5.14. Transceiver Toolkit
6. GTS JESD204C IP Parameters
7. Interface Signals
7.1. Transmitter Signals
7.2. Receiver Signals
8. Control and Status Registers
8.1. Transmitter Registers
8.2. Receiver Registers
9. Document Revision History for the GTS JESD204C IP User Guide

Back to home page