Hard Processor System Booting User Guide - This user guide describes the Agilex™ 3 and Agilex™ 5 SoC boot flow, boot sources, and configuration bitstream generation. - 2026-06-03

Version: 26.1

1. Introduction
1.1. Glossary
1.2. Agilex™ 3 and Agilex™ 5 SoC Boot Overview
2. FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode
2.1.1. Power-On Reset (POR)
2.1.2. Secure Device Manager
2.1.3. First-Stage Bootloader
2.1.4. Second-Stage Bootloader
2.1.5. Operating System
2.1.6. Application
2.2. System Layout for FPGA Configuration First Mode
2.2.1. External Configuration Host Only
2.2.2. External Configuration Host with HPS Flash
2.2.3. Single SDM Flash
2.2.4. FPGA Configuration First - Dual Flash System
3. HPS Boot First Mode
3.1. Boot Flow Overview
3.1.1. Power-On Reset (POR)
3.1.2. Secure Device Manager
3.1.3. First-Stage Bootloader
3.1.4. Second-Stage Bootloader
3.1.5. Operating System
3.1.6. Application
3.2. System Layout for HPS Boot First Mode
3.2.1. External Configuration Host Only
3.2.2. External Configuration Host with HPS Flash
3.2.3. Single SDM Flash
3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.2.1. Device and Pin Options
4.2.2. Platform Designer Options
4.2.3. Generation of Debug HPS FSBL from Hardware Design Build
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.5.1. FPGA Configuration First
4.5.2. HPS Boots First
4.6. Configuration from QSPI
4.6.1. Supported QSPI Devices
4.6.2. FPGA Configuration First
4.6.2.1. Creating Configuration Files from Command Line
4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First
4.6.3.1. Creating Configuration Files from Command Line
4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST
4.7.1. FPGA Configuration First
4.7.1.1. Creating Configuration Files from Command Line
4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First
4.7.2.1. Creating Configuration Files from Command Line
4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol
4.8.1. Creating Configuration Files from Command Line
4.8.2. Creating Configuration Files Using Graphical Interface
4.9. Remote System Update
4.10. Partial Reconfiguration
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.11.1. Data Retention Mechanism Flow
4.11.2. Setting to Enable the Data Retention Mechanism
4.11.3. Preserving Data in SDRAM Across Reset Examples
4.12. QSPI Controller Ownership Selection Impact on the HPS Software
5. HPS Boot Flows
5.1. U-Boot ATF Linux® Boot
5.2. ATF Linux Boot
5.3. ATF Zephyr® Boot
6. Configuring the FPGA Fabric from HPS Software
6.1. Configuring the FPGA Fabric from U-Boot
6.2. Hardware Design Compatibility in HPS Boot First Mode
6.2.1. HPS IO Hash Compatibility
6.2.1.1. Automatic Check of the HPS IO Hash
6.2.1.2. Manual Check of the HPS IO Hash
6.2.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s)
6.2.2.1. IO Configuration Differences on non-HPS EMIF IPs
6.2.2.2. Pin Location Differences
6.2.2.3. PLL Differences
6.2.2.4. Clock Spine Differences
6.2.2.4.1. Agilex™ 5 Specific Clock Spine Differences
6.2.2.4.2. Register Packing Differences
6.2.2.5. HPS IO Hash Mismatch Troubleshooting Examples for HPS EMIF IOs
7. Debugging the Agilex™ 3 and Agilex™ 5 SoC Boot Flow
7.1. Reset
7.1.1. HPS Reset Pin
7.1.2. L4 Watchdog Timer 0
7.2. Debugging the HPS Bootloader
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 3 and Agilex™ 5 SoCs

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