Device Design Guidelines Agilex™ 5 FPGAs and SoCs - Guidelines, recommendations, and a list of factors to consider for designs that use the Agilex 5 SoC devices. - 2025-12-05

Version: 25.3

1. Introduction to Agilex™ 5 Device Design Guidelines
1.1. Design Flow
1.2. Introduction to Agilex™ 5 Device Design Guide Revision History
2. System Specification
2.1. Design Specification
2.2. Install Quartus Prime Software
2.3. IP selection
2.3.1. IP cores
2.3.1.1. Interface Protocol IP cores
2.3.2. HPS IP
2.4. Simulation
2.4.1. RTL Simulation
2.4.2. Simics Simulator
2.5. Preparing for Design Entry
2.5.1. Coding Styles and Design Recommendation
2.5.2. Platform Designer
2.6. I/O Summary
2.7. Using SDM in your devices
2.8. System Specification Revision History
3. Device Selection
3.1. Device Variant
3.1.1. Speed Grade and Package
3.1.2. Power option
3.1.3. Device Migration within Agilex™ 5
3.1.4. PLL
3.1.5. Logic Element, Embedded Memory, and DSP
3.1.6. I/O and LVDS SERDES
3.1.7. MIPI D-PHY
3.1.8. Transceiver
3.1.9. Hard Processor System
3.2. Device Selection Revision History
4. Design Entry
4.1. Design entry for FPGA
4.1.1. Configuration Consideration
4.1.1.1. Partial Reconfiguration
4.1.1.2. SEU
4.1.2. I/O and LVDS SERDES
4.1.2.1. Making FPGA Pin Assignments Checklist
4.1.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device
4.1.2.3. Agilex™ 5 I/O Features and Pin Connections
4.1.2.3.1. I/O Signaling Type
4.1.2.3.2. Selectable Standards and Flexible I/O Banks
4.1.2.3.3. Agilex™ 5 Dual-Purpose and Special Pin Connections
4.1.2.3.4. Agilex™ 5 I/O Features
4.1.3. PLL and Clock Planning
4.1.3.1. Clock and PLL Selection
4.1.3.2. PLL Feature Guidelines
4.1.3.3. Clock Feedback Mode
4.1.3.4. Clock Outputs
4.1.3.5. Clock Control Features
4.1.4. EMIF
4.1.5. Transceiver Planning
4.1.6. Sensors
4.1.6.1. Voltage sensor
4.1.6.2. Temperature Sensor and Temperature Diode
4.1.7. MIPI D-PHY
4.2. Design entry for Nios V
4.3. Design entry for HPS
4.3.1. Simics Simulator
4.3.2. HPS IP Instantiation in Quartus Prime
4.3.3. Embedded Software
4.4. Design Entry Revision History
5. Board and Software consideration
5.1. Early Board Planning
5.1.1. Power - SmartVID or Fixed Voltage
5.1.1.1. Power and Thermal Calculator
5.1.1.2. Power-Up and Power-Down Sequencing
5.1.2. Thermal Management and Design
5.2. Boundary Scan for FPGA and HPS
5.3. Pin Connection Considerations for Board Design
5.3.1. Board-Related Quartus Prime Settings
5.3.1.1. Unused Pins
5.3.2. Signal Integrity Considerations
5.3.2.1. High-Speed Board Design
5.3.2.2. Simultaneous Switching Noise
5.3.2.3. I/O Termination
5.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
5.4. Planning for Device Configuration
5.4.1. Device Power Cycling and Reconfiguration
5.4.2. Configuration Scheme Selection
5.4.2.1. Serial Configuration Devices
5.4.2.2. Intel FPGA Download Cable II
5.4.3. Configuration Features
5.4.4. Quartus Prime Configuration Settings
5.4.4.1. Optional Configuration Pins
5.4.4.2. Dual Purpose Configuration Pins
5.4.5. Configuration Pin Connections
5.4.5.1. Configuration Pin Voltage Level
5.4.5.2. Clock Trace Signal Integrity
5.4.6. JTAG Pins
5.4.6.1. JTAG Pin Connections
5.4.6.2. JTAG Signal Buffering
5.4.6.3. Download Cable Operating Voltage
5.4.7. MSEL Configuration Mode Pins
5.4.8. Other Configuration Pins
5.5. Board and Software Consideration Revision History
6. Design Implementation, Analysis, Optimization and Verification
6.1. Synthesis Tool
6.2. Device Resource Reports
6.3. Quartus Prime Message
6.4. Design Assistant Design Rule Checking
6.5. Timing Constraints and Analysis
6.5.1. Recommended Timing Optimization and Analysis Assignments
6.5.2. SDC-on-RTL and Post-Synthesis Static Timing Analysis
6.6. Area and Timing Optimization
6.7. Preserving Performance and Reducing Compilation Time
6.8. Designing with Hyperflex
6.9. Simulation
6.10. Power Analysis
6.11. Design Implementation, Analysis, Optimization and Verification Revision History
7. Debugging
7.1. On-Chip Debug Overview
7.2. On-Chip Debugging Tools
7.3. Debugging Revision History

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