Clocking and PLL User Guide Agilex™ 5 FPGAs and SoCs - Describes the Agilex 5 device programmable clock routing network and I/O PLLs for clock management and synthesis. Includes information about the Clock Control FPGA IP and IOPLL FPGA IP . - 2026-03-30
- Version
- 25.1.1
- Product Type
- Device Families > Agilex Families > Agilex 5
- Device Families > Agilex Families > Agilex 5 > D-Series
- Device Families > Agilex Families > Agilex 5 > E-Series
- Device Families > Agilex Families
- Resource Type
- Documentation > User Guides
- Source Name
- DITA