Low Latency Ethernet 10G MAC IP Design Example User Guide Agilex™ 3 and Agilex™ 5 FPGAs and SoCs - Describes the Low Latency Ethernet 10G MAC IP design examples for Agilex 3 and Agilex 5 devices. These design examples generate the necessary files to simulate, compile, and test the designs in hardware. - 2026-01-05

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25.3.1