Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs - Describes the features and functions of this IP core for Agilex™ 5 devices. The IP implements the Ethernet protocol as defined in the IEEE 802.3 2005 Standard and consists of a physical coding sublayer (PCS) function and an embedded physical media attachment (PMA). - 2024-07-16

Version

24.2-2.1.0