Low Latency Ethernet 10G MAC IP User Guide Agilex™ 3 and Agilex™ 5 FPGAs and SoCs - Describes the features, functions, and signals of the Low Latency Ethernet 10G MAC IP for Agilex 3 and Agilex 5 devices. The IP allows you to build a complete Ethernet subsystem in an Intel FPGA device and connect it to an external device using the IP with an Intel FPGA PHY IP core or any of the supported PHYs. - 2026-01-05

Version

25.3.1