AN 985: Nios V Processor Tutorial - This document provides a getting started guide to build a Nios V processor system that runs a simple Hello World software. - 2026-01-07

1. AN 985: Nios V Processor Tutorial
1.1. Overview
2. Hello World on Agilex™ 7 FPGA F-Series Transceiver-SoC Development Kit
2.1. Hardware and Software Requirements
2.2. Generating the System
2.2.1. Building Hardware Design in Platform Designer Overview
2.2.2. Building Hardware Design in Platform Designer — Manual Instantiation
2.2.2.1. Creating a New Project
2.2.2.2. Creating a Platform Designer System
2.2.2.2.1. Adding Nios V/m Processor IP
2.2.2.2.2. Adding On-Chip Memory II (RAM or ROM) IP
2.2.2.2.3. Adding JTAG UART IP
2.2.2.2.4. Adding Reset Release IP
2.2.2.2.5. Connect Interfaces and Signals
2.2.2.2.6. Clear System Warnings and Errors
2.2.2.2.7. Configuring the Reset Vector of the Nios V Processor
2.2.2.2.8. Saving and Generating System HDL
2.2.2.3. Configuring Assignment and Constraint
2.2.2.3.1. Adding Design Files
2.2.2.3.2. Adding Synopsys Design Constraint (SDC) File
2.2.2.3.3. Pin Assignments
2.2.2.3.4. Configuration and Power Management Assignments
2.2.2.4. Compiling the Quartus Prime Software Project
2.2.3. Building Hardware Design in Platform Designer — Board-Aware Flow
2.2.3.1. Creating a New Project
2.2.3.2. Creating a Platform Designer System
2.2.3.2.1. Adding Nios V/m Processor IP
2.2.3.2.2. Adding On-Chip Memory (RAM or ROM) IP
2.2.3.2.3. Adding JTAG UART IP
2.2.3.2.4. Adding System ID Peripheral IP
2.2.3.2.5. Adding Reset Release IP
2.2.3.2.6. Connect Interfaces and Signals
2.2.3.2.7. Clear System Warnings and Errors
2.2.3.2.8. Saving and Generating System HDL
2.2.3.3. Configuring Assignment and Constraint
2.2.3.3.1. Adding Design Files
2.2.3.3.2. Adding Synopsys Design Constraint (SDC) File
2.2.3.3.3. Pin Assignments
2.2.3.3.4. Configuration and Power Management Assignments
2.2.3.4. Compiling the Quartus Prime Software Project
2.2.4. Building Hardware Design in Platform Designer — Configurable Example Design
2.2.4.1. Creating a New Project
2.2.4.2. Creating a Platform Designer System
2.2.4.2.1. Saving and Generating System HDL
2.2.4.3. Configuring Assignment and Constraint
2.2.4.3.1. Adding Design Files
2.2.2.3.3. Pin Assignments
2.2.2.3.4. Configuration and Power Management Assignments
2.2.2.4. Compiling the Quartus Prime Software Project
2.2.5. Building Software Design with Ashling RiscFree IDE for Altera FPGAs
2.2.5.1. Creating a Board Support Package
2.2.5.2. Creating an Application Project File
2.2.5.3. Importing Projects into Ashling RiscFree IDE for Altera FPGAs
2.2.5.3.1. Importing Nios V Processor BSP Project
2.2.5.3.2. Importing Application Project
2.2.5.3.3. Establishing Dependencies
2.2.5.4. Building the Hello World Application
2.3. Simulating the Nios V Processor System
2.3.1. Preparing Hardware Design for Simulation
2.3.2. Preparing Software Design for Simulation
2.3.3. Checking Simulation Files
2.3.4. Running System Simulation
2.4. Programming the System
2.4.1. Programming Hardware SOF File
2.4.2. Downloading the Software ELF File
2.4.3. Applying External Tool Configuration
2.4.4. Run Hello World Application
2.5. Debugging the System
2.5.1. Software Debugging
2.5.1.1. Setting Initial Breakpoint
2.5.1.2. Starting the Debugger
2.5.1.3. View Global Variables
2.5.1.4. View Memory
2.5.1.5. Setting a Second Breakpoint
2.5.1.6. Control Debugger
3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit
3.1. Hardware and Software Requirements
2.2. Generating the System
3.2.1. Building Hardware Design in Platform Designer
3.2.1.1. Creating a New Project
3.2.1.2. Creating a Platform Designer System
3.2.1.3. Configuring Assignment and Constraint
2.2.2.4. Compiling the Quartus Prime Software Project
3.2.2. Building Software Design with Ashling RiscFree IDE for Altera FPGAs
3.2.2.1. Creating a Board Support Package
3.2.2.2. Creating an Application Project Files
2.2.5.3. Importing Projects into Ashling RiscFree IDE for Altera FPGAs
2.2.5.3.1. Importing Nios V Processor BSP Project
2.2.5.3.2. Importing Application Project
3.2.2.3.3. Establishing Dependencies
3.2.2.4. Building the Hello World Application
2.3. Simulating the Nios V Processor System
3.3.1. Preparing Hardware Design for Simulation
2.3.2. Preparing Software Design for Simulation
3.3.3. Checking Simulation Files
2.3.4. Running System Simulation
2.4. Programming the System
3.4.1. Programming Hardware SOF File
3.4.2. Downloading the Software ELF File
2.4.3. Applying External Tool Configuration
2.4.4. Run Hello World Application
2.5. Debugging the System
3.5.1. Software Debugging
2.5.1.1. Setting Initial Breakpoint
3.5.1.2. Starting the Debugger
2.5.1.3. View Global Variables
2.5.1.4. View Memory
3.5.1.5. Setting a Second Breakpoint
2.5.1.6. Control Debugger
4. Document Revision History for the AN 985: Nios V Processor Tutorial

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