High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide - The Ethernet Subsystem Intel® FPGA IP for Agilex™ 7 (F-Tile and E-Tile) device is a subsystem IP that includes a configurable, hardened protocol stack for Ethernet. - 2024-04-29

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24.1-4.0.0