AN 978: Nios V Processor Migration Guidelines - Describes the guidelines for migrating from the Nios II processor to the corresponding Nios V processor core. - 2026-01-07

1. Overview
2. Architecture Comparison
2.1. Features Comparison
2.2. Ecosystem Comparison
2.3. Software Optimization
3. Processor Core Upgrade Paths
4. Design Flow Comparison
4.1. Differences in the Design Flow
4.2. Design Upgrade from Nios II Processor to Nios V Processor
4.2.1. Quartus Prime Standard Edition
4.2.1.1. Hardware Component
4.2.1.2. Software Component
4.2.2. Quartus Prime Pro Edition
4.2.2.1. Hardware Component
4.2.2.2. Software Component
5. Processor Core Comparison
5.1. Upgrading Nios II/e Processor to Nios V/c Processor
5.1.1. Hardware Perspective
5.1.1.1. Signal and Interface Mapping
5.1.1.2. IP Parameter Configuration
5.1.1.3. BSP Project Generation
5.1.2. Software Perspective
5.1.2.1. Command-Line Build Flow
5.1.2.2. IDE Build Flow
5.2. Upgrading Nios II Processor to Nios V/m Processor
5.2.1. Hardware Perspective
5.2.1.1. Signal and Interface Mapping
5.2.1.2. IP Parameter Configuration
5.1.1.3. BSP Project Generation
5.2.2. Software Perspective
5.1.2.1. Command-Line Build Flow
5.1.2.2. IDE Build Flow
5.3. Upgrading Nios II/f Processor to Nios V/g Processor
5.3.1. Hardware Perspective
5.3.1.1. Signal and Interface Mapping
5.3.1.2. IP Parameter Configuration
5.3.1.3. BSP Project Generation
5.2.2. Software Perspective
5.3.2.1. Command-Line Build Flow
5.3.2.2. IDE Build Flow
6. Feature Comparison
6.1. Timer
6.2. Interrupt
6.3. Shadow Register
6.4. Ethernet Stack
6.5. Bootloader
6.6. Data and Instruction Cache
6.7. Tightly Coupled Memory
6.8. Custom Instructions
6.9. Error Correction Code
6.10. Altera HAL Settings
6.11. Micrium MicroC/OS-II BSP Settings
6.12. Software Packages
7. Assembly Language Comparison
7.1. Arithmetic and Logic Operations
7.2. Data Handling and Memory Operations
7.3. Control Flow Operations
7.4. Miscellaneous Operations
8. Document Revision History for the AN 978: Nios V Processor Migration Guidelines

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