Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide - Describes the features, signals, and parameters of the F-Tile Triple-Speed Ethernet Intel® FPGA IP. The F-Tile Triple-Speed Ethernet Intel® FPGA IP is a configurable intellectual property (IP) that incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os. - 2024-05-15

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24.1