Nios V Embedded Processor Design Handbook - The handbook describes how to most effectively use the tools, and recommends design styles and practices for developing, debugging, and optimizing embedded systems using the Nios V processor and Altera -provided tools. - 2026-04-06
Version
26.1
Product Type
Device Families > Agilex Families > Agilex 5
Device Families > Agilex Families > Agilex 5 > E-Series
Device Families > Agilex Families
Device Families > Cyclone Families > Cyclone IV
Device Families > Agilex Families > Agilex 7
Device Families > Agilex Families > Agilex 3
Device Families > Stratix Families > Stratix IV
Device Families > Stratix Families
Device Families > Cyclone Families > Cyclone V
Device Families > Stratix Families > Stratix V
Device Families > Agilex Families > Agilex 7 > I-Series
Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 GX
Device Families > Arria Families > Arria V
Device Families > Cyclone Families > Cyclone 10
Device Families > Agilex Families > Agilex 5 > D-Series
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Arria Families > Arria II
Device Families > Arria Families > Arria 10
Device Families > MAX Families > MAX 10
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 LP
Device Families > Stratix Families > Stratix 10
Device Families > Cyclone Families
Device Families > Arria Families
Development Software and Tools > Embedded Design Tools & Software > Nios V
Device Families > MAX Families
Device Families > Agilex Families > Agilex 3 > C-Series
Resource Type
Documentation > User Guides
Source Name
DITA
1. About the Nios V Embedded Processor
1.1. Altera FPGA and Embedded Processors Overview
1.2. Quartus Prime Software Support
1.3. Nios V Processor Licensing
1.4. Embedded System Design
1.5. Recommended Tools from Quartus Prime Installer
1.5.1. Embedded FPGA Hardware and Software Developer
1.5.2. Embedded FPGA Hardware Developer
1.5.3. Embedded FPGA Software Developer
2. Nios V Processor Hardware System Design with Quartus Prime Software and Platform Designer
2.1. Creating Nios V Processor System Design with Platform Designer
2.1.1. Instantiating Nios V Processor Altera FPGA IP
2.1.1.1. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP
2.1.1.1.1. CPU Architecture Tab
2.1.1.1.2. Use Reset Request Tab
2.1.1.1.3. Traps, Exceptions, and Interrupts Tab
2.1.1.1.4. ECC Tab
2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP
2.1.1.2.1. Debug Tab
2.1.1.2.2. Use Reset Request Tab
2.1.1.2.3. Traps, Exceptions, and Interrupts Tab
2.1.1.2.4. CPU Architecture
2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios V/g General Purpose Processor Altera FPGA IP
2.1.1.3.1. CPU Architecture
2.1.1.2.1. Debug Tab
2.1.1.3.3. Lockstep Tab
2.1.1.2.2. Use Reset Request Tab
2.1.1.3.5. Traps, Exceptions, and Interrupts Tab
2.1.1.3.6. Memory Configurations Tab
2.1.1.3.7. ECC Tab
2.1.1.3.8. Custom Instruction Tab
2.1.2. Defining System Component Design
2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.4. Enabling RISC-V based Debug Module
2.1.5. Enabling Timer and Software Interrupts
2.2. Clocks and Resets Best Practices
2.2.1. System JTAG Clock
2.2.2. Reset Request Interface
2.2.2.1. Typical Use Cases
2.2.3. Reset Release IP
2.3. Designing a Nios V Processor Memory System
2.3.1. Volatile Memory
2.3.1.1. On-Chip Memory Configuration – RAM or ROM
2.3.1.2. Caches
2.3.1.2.1. Peripheral region
2.3.1.3. Tightly Coupled Memory
2.3.1.3.1. Default Use Case – Read-only Instruction TCM
2.3.1.3.2. Debug Use Case – Read and Write Capable Instruction TCM
2.3.1.4. External Memory Interface (EMIF)
2.3.1.4.1. Address Span Extender IP
2.3.1.4.2. Using Address Span Extender IP with Nios V Processor
2.3.1.4.3. Defining Address Span Extender Linker Memory Device
2.3.2. Non-Volatile Memory
2.4. Assigning a UART Agent for Printing
2.4.1. Preventing Stalls by the JTAG UART
2.5. Assigning a Default Agent
2.6. Understanding the Design Requirement with JTAG Signals
2.7. Optimizing Platform Designer System Performance
2.7.1. Precaution on Adding Avalon Memory Mapped Pipeline Bridge
2.8. Integrating Platform Designer System into the Quartus Prime Project
2.8.1. Instantiating the Nios V Processor System Module in the Quartus Prime Project
2.8.2. Connecting Signals and Assigning Physical Pin Locations
2.8.3. Constraining the Altera FPGA Design
2.9. Handing Off to an Embedded FPGA Software Developer
3. Nios V Processor Software System Design
3.1. Receiving from Embedded FPGA Hardware Developer
3.2. Nios V Processor Software Development Flow
3.2.1. Board Support Package Project
3.2.2. Application Project
3.3. Altera FPGA Embedded Development Tools
3.3.1. Nios V Processor Board Support Package Editor
3.3.2. RiscFree IDE for Altera FPGAs
3.3.3. Nios V Utilities Tools
3.3.4. File Format Conversion Tools
3.3.5. Other Utilities Tools
4. Nios V Processor Debugging, Verifying, and Simulating
4.1. Debugging Nios V/c Processor
4.1.1. Pilot System with Non-pipelined Nios V/m Processor
4.1.2. printf() Debugging
4.2. Debugging Nios V Processor Hardware Designs
4.2.1. JTAG Server
4.2.1.1. Identifying Processor Instances from Multicore Designs
4.2.2. System Console
4.2.2.1. JTAG to Avalon Host Bridge Core
4.2.3. Signal Tap Logic Analyzer with Nios V Processor Signal Tap Plugin
4.2.3.1. Hardware and Software Requirements
4.2.3.2. Setting Up Signal Tap Logic Analyzer
4.2.3.2.1. Enabling Signal Tap Logic Analyzer
4.2.3.2.2. Adding Signals for Monitoring and Debugging
4.2.3.2.3. Specifying Trigger Conditions
4.2.3.2.3.1. Basic Trigger Conditions
4.2.3.2.3.2. Power-Up Trigger Conditions
4.2.3.2.3.3. Other Trigger Conditions
4.2.3.2.3.4. No Trigger Conditions
4.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
4.2.3.2.5. Compiling the Design and Programming the Target Device
4.2.3.3. Running the Capture Session
4.2.3.3.1. Performing Data Capture with Ashling RiscFree IDE for Altera FPGAs
4.2.3.3.2. Performing Data Capture Without Software Download
4.2.3.4. Analyzing Results
4.2.3.4.1. Viewing Data
4.2.3.4.2. Correlating Trace Data to Software ELF
4.2.3.4.3. Saving and Converting Captured Data
4.2.4. In-System Sources and Probes
4.3. Debugging Nios V Processor Software Designs
4.3.1. Ashling RiscFree IDE for Altera FPGAs
4.3.2. Ashling Visual Studio Code Extension for Altera FPGAs
4.3.3. OpenOCD
4.3.4. Objdump File
4.3.5. Show Make Commands
4.4. Debugging Tools
4.5. Additional Embedded Design Considerations
4.5.1. JTAG Signal Integrity
4.5.2. Additional Memory Space for System Prototyping
4.6. Simulating Nios V Processor Designs
4.6.1. Prerequisites
4.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
4.6.2.1. Using IP and Platform Designer Simulation Setup Scripts
4.6.3. Creating Nios V Processor Software
4.6.3.1. Generating the Board Support Package
4.6.3.2. Generating the Application Project File
4.6.3.3. Building the Application Project
4.6.4. Generating Memory Initialization File
4.6.5. Generating System Simulation Files
4.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
5. Nios V Processor Configuration and Booting Solutions
5.1. Introduction
5.2. Linking Applications
5.2.1. Linking Behavior
5.2.1.1. Default BSP Linking
5.2.1.2. Configurable BSP Linking
5.3. Nios V Processor Booting Methods
5.4. Introduction to Nios V Processor Booting Methods
5.4.1. Nios V Processor Application Execute-In-Place from Boot Flash
5.4.1.1. alt_load()
5.4.2. Nios V Processor Application Copied from Boot Flash to RAM Using Boot Copier
5.4.2.1. Nios V Processor Bootloader via Generic Serial Flash Interface
5.4.2.2. Nios V Processor Bootloader via Secure Device Manager
5.4.3. Nios V Processor Application Execute-In-Place from OCRAM
5.4.4. Nios V Processor Application Execute-In-Place from TCM
5.5. Nios V Processor Booting from On-Chip Flash (UFM)
5.5.1. MAX 10 FPGA On-Chip Flash Description
5.5.2. Nios V Processor Application Execute-In-Place from UFM
5.5.2.1. Hardware Design Flow
5.5.2.2. Software Design Flow
5.5.2.3. Programming
5.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier
5.5.3.1. Hardware Design Flow
5.5.3.2. Software Design Flow
5.5.3.3. Programming
5.6. Nios V Processor Booting from General Purpose QSPI Flash
5.6.1. Nios V Processor Application Executes-In-Place from General Purpose QSPI Flash
5.6.1.1. Hardware Design Flow
5.6.1.2. Software Design Flow
5.6.1.3. Programming Files Generation
5.6.1.4. QSPI Flash Programming
5.6.2. Nios V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI)
5.6.2.1. Hardware Design Flow
5.6.2.2. Software Design Flow
5.6.2.3. Programming Files Generation
5.6.2.4. QSPI Flash Programming
5.7. Nios V Processor Booting from Configuration QSPI Flash
5.7.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device)
5.7.1.1. Nios V Processor Application Executes-In-Place from Configuration QSPI Flash
5.7.1.1.1. Hardware Design Flow
5.7.1.1.2. Software Design Flow
5.7.1.1.3. Programming Files Generation
5.7.1.1.4. QSPI Flash Programming
5.7.1.2. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI)
5.7.1.2.1. Hardware Design Flow
5.7.1.2.2. Software Design Flow
5.7.1.2.3. Programming Files Generation
5.7.1.2.4. QSPI Flash Programming
5.7.1.3. Bootloader via GSFI Example Design
5.7.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
5.7.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM)
5.7.2.1.1. Hardware Design Flow
5.7.2.1.2. Software Design Flow
5.7.2.1.3. Software Design Flow (Bootloader via SDM Project)
5.7.2.1.4. Software Design Flow (User Application Project)
5.7.2.1.5. Programming Files Generation
5.7.2.1.6. QSPI Flash Programming SDM
5.7.2.2. Bootloader via SDM Example Design
5.8. Nios V Processor Booting from On-Chip Memory (OCRAM)
5.8.1. Nios V Processor Application Executes in-place from OCRAM
5.8.1.1. Hardware Design Flow
5.8.1.2. Software Design Flow
5.8.1.3. Programming
5.9. Nios V Processor Booting from Tightly Coupled Memory (TCM)
5.9.1. Nios V Processor Application Executes in-place from TCM
5.9.1.1. Hardware Design Flow
5.9.1.2. Software Design Flow
5.9.1.3. Programming
5.10. Summary of Nios V Processor Vector Configuration and BSP Settings
5.11. Reducing Nios V Processor Booting Time
5.11.1. Boot Methods
5.11.2. Boot devices
5.11.3. Peripheral Initialization
5.11.4. Caches
5.11.5. System Speed
6. Finding Nios V Processor Design Example
6.1. Altera FPGA Developer Site
6.2. FPGA Design Store
7. Nios V Processor - Using the MicroC/TCP-IP Stack
7.1. Introduction
7.2. Software Architecture
7.3. Support and Licensing
7.4. MicroC/TCP-IP Example Designs
7.4.1. Hardware and Software Requirements
7.4.2. Overview
7.4.3. Acquiring the Example Design Files
7.4.4. Hardware Design Files
7.4.5. Software Design Files
7.4.5.1. MicroC/TCP-IP IPerf Example Design
7.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
7.5. Development Flow
7.5.1. Hardware Development Flow
7.5.2. Software Development Flow
7.5.2.1. Creating a BSP project
7.5.2.2. Configuring the BSP
7.5.2.3. Creating an Application Project
7.5.2.4. Building the Application Project
7.5.3. Device Programming
7.6. Operating the Example Designs
7.6.1. Operating the MicroC/TCP-IP IPerf
7.6.2. Operating the MicroC/TCP-IP Simple Socket Server
7.7. Optional Configuration
7.7.1. Configuring Hardware Name
7.7.2. Configuring MAC and IP Addresses
7.7.3. Configuring MicroC/TCP-IP Initialization
7.7.3.1. Network Task Configuration
7.7.3.2. Network Interface Configuration
7.7.4. Configuring iPerf Server Auto-Initialization
7.8. MicroC/TCP-IP Simple Socket Server Concepts
7.8.1. MicroC/OS-II Resources
7.8.2. Error Handling
7.8.3. MicroC/TCP-IP Stack Default Configuration
8. Nios V Processor — Remote System Update
8.1. Overview
8.2. Quartus Prime Pro Edition Software and Tool Support
8.2.1. Quartus Prime Pro Edition Software
8.2.1.1. Setting Max Retry Parameter
8.2.1.2. Selecting Factory Load Pin
8.2.2. Programming File Generator
8.2.2.1. Programming File Generator File Types
8.2.2.2. Bitswap Option
8.2.2.3. Quartus Prime Programmer
8.2.2.4. Supported QSPI Flash Devices
8.3. Nios V Processor RSU Quick Start Guide in SDM-based Devices
8.3.1. Individual Factory, Application, and Update Images
8.3.2. Hardware Design Flow
8.3.2.1. Create a Platform Designer System
8.3.2.2. Quartus Prime Software Settings
8.3.3. Software Design Flow
8.3.3.1. Generating the ZLIB libraries
8.3.3.2. Creating a Board Support Package Project
8.3.3.3. Configuring and Generating the BSP Project
8.3.3.4. Creating Multiple Application Projects
8.3.3.5. Building the Application Projects
8.3.3.6. Generating HEX Files
8.3.4. Individual Images Generation
8.3.5. Remote System Update Image Files Generation
8.3.5.1. Generating Initial RSU Image Using SOF file
8.3.5.2. Generating an Application Update Image
8.3.5.3. Generating a Factory Update Flash Image
8.3.6. QSPI Flash Programming
8.3.6.1. Programming the Initial RSU Image
8.3.6.2. Programming the Update Images
8.3.7. Operating the RSU Client API
8.3.7.1. Trigger Reconfiguration Menu with Selected Image
8.3.7.2. Updating an Application Image
8.3.7.3. Updating the Factory Image
9. Nios V Processor – Running TinyML Application
10. Nios V Processor – Implementing Lockstep Capabilities
11. Nios V Processor — Using Custom Instruction
12. Document Revision History for the Nios V Embedded Processor Design Handbook