Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide - Hard IP for PCI Express Endpoint and Root Port, Gen1, Gen2, Gen3 - 2017-05-21

Version: 15.1

1. Datasheet
1.1. Arria V GZ Avalon-MM Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Design Examples
1.7. Debug Features
1.8. IP Core Verification
1.8.1. Compatibility Testing Environment
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
2. Getting Started with the Avalon-MM Design Example
2.1. Running Qsys
2.2. Generating the Example Design
2.3. Understanding Simulation Log File Generation
2.4. Running a Gate-Level Simulation
2.5. Simulating the Single DWord Design
2.6. Generating Synthesis Files
2.7. Creating a Quartus Prime Project
2.8. Compiling the Design
2.9. Programming a Device
2.10. Understanding Channel Placement Guidelines
3. Parameter Settings
3.1. System Settings
3.2. Base Address Register (BAR) Settings
3.3. Device Identification Registers
3.4. PCI Express and PCI Capabilities Parameters
3.4.1. Device Capabilities
3.4.2. Error Reporting
3.4.3. Link Capabilities
3.4.4. MSI and MSI-X Capabilities
3.4.5. Power Management
3.5. Avalon Memory‑Mapped System Settings
4. 64- or 128-Bit Avalon-MM Interface to the Application Layer
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
4.2. RX Avalon-MM Master Signals
4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.4. Clock Signals
4.5. Reset
4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled
4.7. Hard IP Status Signals
4.7.1. Hard IP Reconfiguration Interface
4.7.2. Configuration Space Register Access Timing
4.7.3. Configuration Space Register Access
4.8. Physical Layer Interface Signals
4.8.1. Hard IP Status Extension
4.8.2. Serial Data Signals
4.8.2.1. Physical Layout of Hard IP in Arria V GZ Devices
4.8.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
4.8.3. PIPE Interface Signals
4.8.4. Test Signals
5. Registers
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Altera-Defined VSEC Registers
5.6. CvP Registers
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers
5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
5.7.1.3. PCI Express Mailbox Registers
5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table
5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
5.7.1.6. Avalon-MM Mailbox Registers
5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port
5.8.1. Sending a Write TLP
5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP
5.8.3. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
5.8.4. Root Port TLP Data Registers
5.9. Uncorrectable Internal Error Mask Register
5.10. Uncorrectable Internal Error Status Register
5.11. Correctable Internal Error Mask Register
5.12. Correctable Internal Error Status Register
6. Reset and Clocks
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
6.2. Clocks
6.2.1. Clock Domains
6.2.1.1. pclk
6.2.1.2. coreclkout_hip
6.2.1.3. pld_clk
6.2.2. Clock Summary
7. Interrupts for Endpoints
7.1. Enabling MSI or Legacy Interrupts
7.2. Generation of Avalon-MM Interrupts
7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling
8.1. Physical Layer Errors
8.2. Data Link Layer Errors
8.3. Transaction Layer Errors
8.4. Error Reporting and Data Poisoning
8.5. Uncorrectable and Correctable Error Status Bits
9. IP Core Architecture
9.1. Top-Level Interfaces
9.2. Avalon-MM Interface
9.3. Clocks and Reset
9.4. Transceiver Reconfiguration
9.5. Interrupts
9.6. PIPE
9.7. Data Link Layer
9.8. Physical Layer
9.9. 32-Bit PCI Express Avalon-MM Bridge
9.9.1. Avalon‑MM Bridge TLPs
9.9.2. Avalon-MM-to-PCI Express Write Requests
9.9.3. Avalon-MM-to-PCI Express Upstream Read Requests
9.9.4. PCI Express-to-Avalon-MM Read Completions
9.9.5. PCI Express-to-Avalon-MM Downstream Write Requests
9.9.6. PCI Express-to-Avalon-MM Downstream Read Requests
9.9.7. Avalon-MM-to-PCI Express Read Completions
9.9.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
9.9.9. Minimizing BAR Sizes and the PCIe Address Space
9.9.10. Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
9.10. Completer Only Single Dword Endpoint
9.10.1. RX Block
9.10.2. Avalon-MM RX Master Block
9.10.3. TX Block
9.10.4. Interrupt Handler Block
10. Transceiver PHY IP Reconfiguration
10.1. Connecting the Transceiver Reconfiguration Controller IP Core
10.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
11. Design Implementation
11.1. Making Analog QSF Assignments Using the Assignment Editor
11.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins
11.3. Recommended Reset Sequence to Avoid Link Training Issues
11.4. SDC Timing Constraints
12. Throughput Optimization
12.1. Throughput of Posted Writes
12.2. Throughput of Non-Posted Reads
13. Optional Features
13.1. Configuration over Protocol (CvP)
13.2. Autonomous Mode
13.2.1. Enabling Autonomous Mode
13.2.2. Enabling CvP Initialization
13.3. ECRC
13.3.1. ECRC on the RX Path
13.3.2. ECRC on the TX Path
14. Debugging
14.1. Hardware Bring-Up Issues
14.2. Link Training
14.2.1. Debugging Link that Fails To Reach L0
14.3. Use Third-Party PCIe Analyzer
14.4. BIOS Enumeration Issues
14.5. Changing Between Serial and PIPE Simulation
A. Lane Initialization and Reversal
B. Revision History
B.1. Revision History for the Avalon-MM Interface

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