2.8. PMA Avalon Memory-Mapped Signals - 2025-12-15

F-Tile PMA and FEC Direct PHY Multirate IP User Guide
Version
24.3.1

The following table describes the PMA Avalon® memory-mapped signals that are a part of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.

Table 15.  PMA Avalon® Memory-Mapped Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for full variable definitions.
Signal Name Clocks Domain/Resets Direction Description
reconfig_xcvr_clk N/A Input Reconfiguration Interface Clock
reconfig_xcvr_reset reconfig_xcvr_clk Input PMA reconfiguration interface reset. You must assert this reset at least once after power on.
reconfig_xcvr_address[17+K p:0] reconfig_xcvr_clk Input Reconfiguration Interface Address K p=Ceiling(log2(N)). Upper address bits are for shared PMA decoding if more than one PMA exists.
reconfig_xcvr_byteenable[3:0] reconfig_xcvr_clk Input Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword Access; otherwise uses byte access.
reconfig_xcvr_write reconfig_xcvr_clk Input Reconfiguration Write
reconfig_xcvr_read reconfig_xcvr_clk Input Reconfiguration Read
reconfig_xcvr_writedata[31:0] reconfig_xcvr_clk Input Reconfiguration Write data
reconfig_xcvr_readdata[31:0] reconfig_xcvr_clk Output Reconfiguration Read data
reconfig_xcvr_waitrequest reconfig_xcvr_clk Output Reconfiguration Wait Request
reconfig_xcvr_readdatavalid reconfig_xcvr_clk Output Reconfiguration Read Data Valid. Optional port, available if the port is enabled in parameter editor.