This section describes the QSF settings required for dynamic reconfiguration to work for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.
General QSF Settings
The following table describes the general QSF setting that is required and its use.| QSF Settings | Description |
|---|---|
| set_instance_assignment -name IP_COLOCATE F_TILE -from <hpath1> -to <hpath2> -entity <top_level_name> |
Associates a Dynamic Reconfiguration Controller with the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP that it is controlling. The <hpath1> is the hierarchy path of the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP in your design and <hpath2> is the hierarchy path of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP in your design. |
Note: Refer to Dynamic Reconfiguration QSF Settings in the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide for the relevant .qsf assignments.
The following example .qsf assignment illustrates the setting for a design using the F-Tile PMA/FEC Direct PHY Multirate
Intel® FPGA IP:
set_instance_assignment -name IP_COLOCATE F_TILE -from dr_dut|dr_f_0 \ -to dut|directphy_f_dr_0