The following table describes the Custom Cadence control and status signals that are a part of the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.
| Signal Name | Clocks Domain/Resets | Direction | Description |
|---|---|---|---|
| tx_cadence[m] |
tx_cadence_fast_clk_fracture[m] tx_reset[m] |
Output | This signal indicates the rate at which tx data valid must be asserted and deasserted when the system is running at a higher clock rate than the PMA word/bond clock. |
| tx_cadence_fast_clk_fracture[m] | N/A | Input | Fast clock input for tx_cadence generator. Use this as the system clock within F-tile (or use (system clock)/2 when Core Interface is in double width mode). |
| tx_cadence_slow_clk_fracture[m] | N/A | Input | Slow clock input for tx_cadence generator. Use this clock as the PMA word/bond clock (or (PMA word/bond clock)/2 when Core Interface is in double width mode). |