2.5. Signal Tap Debugging - The IP provides a list of predefined debug signals to capture the behavior of the design example components. - 2025-12-15

F-Tile Low Latency Ethernet 10G MAC IP Design Example User Guide
Version
24.3.1
The IP provides a list of predefined debug signals to capture the behavior of the design example components.
To program the hardware design example on Agilex™ 7 devices:
  1. Click Tools > Signal Tap Logic Analyzer.
  2. Click Hardware Setup and select respective hardware for programming.
  3. Click on Scan Chain to select the proper JTAG.
  4. Click on the SOF Manager to browse and program the SOF.
  5. After the programming is complete, click any of the signals under the Setup window to view the signal behavior.
  6. In the Instance Manager toolbar, click Run Analysis. The signal capture and signal transitions is displayed in the Data window.
  7. Refer to the Signal Tap Logic Analyzer Introduction for more information about Signal Tap.
To start the signal tap debugging:
  1. Generate the design example for the Low Latency Ethernet 10G MAC IP.
  2. Open the .qpf file in the intel_eth_em10g32_0_EXAMPLE_DESIGN/LL10G_10G_USXGMII/ directory.
  3. In the Quartus® Prime Pro Edition software, click File > Open > <LL10G_10G_USXGMII*> > *.stp
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