2.3. Compiling and Simulating the Design - 2025-12-15

F-Tile Low Latency Ethernet 10G MAC IP Design Example User Guide

Version: 24.3.1

1. About the F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide
2. Quick Start Guide
2.1. Directory Structure
2.2. Generating the Design
2.2.1. Procedure
2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design
2.3.1. Procedure
2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware
2.4.1. Procedure
2.4.2. Hardware Setup
2.5. Signal Tap Debugging
2.5.1. Signal Tap Debug Signals
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
3.1. Features
3.2. Hardware and Software Requirements
3.3. Functional Description
3.3.1. Design Components
3.3.2. Clocking Scheme
3.3.3. Reset Scheme
3.3.3.1. Reset Sequence
3.3.3.1.1. Run-time Reset Sequence—TX
3.3.3.1.2. Run-time Reset Sequence—RX
3.3.3.1.3. Run-time Reset Sequence—TX + RX
3.4. Simulation
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing
3.5.1. Test Procedure
3.5.2. Design Constraints
3.6. Interface Signals
3.7. Configuration Registers
4. Interface Signals Description
4.1. Clock and Reset Interface Signals
4.2. Avalon Memory-Mapped Interface Signals
4.3. Avalon Streaming Interface Signals
4.4. PHY Interface Signals
4.5. Status Interface
4.6. IEEE 1588v2 Timestamp Interface Signals
4.7. Packet Classifier Interface Signals
4.8. TOD Interface Signals
5. Configuration Registers Description
5.1. Register Access Definition
5.2. Low Latency Ethernet 10G MAC
5.3. PHY
5.3.1. 1G/2.5G/5G/10G Multirate PHY
5.4. TOD
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide

Back to home page