4.4. Symmetric Cryptographic Accelerator Hard IP Flow - This section describes the generic flow for the Symmetric Cryptographic Accelerator Hard IP . - 2026-02-24

Symmetric Cryptographic Accelerator Hard IP User Guide
Version
25.3
This section describes the generic flow for the Symmetric Cryptographic Accelerator Hard IP.
To enable the flow, the FPGA must enter user mode and the AES/SM4 Inline Cryptographic Accelerator is in the user configuration state.
  1. Drive all the clocks into the Symmetric Cryptographic Accelerator Hard IP.
  2. Set the bits to deassert resets to the Symmetric Cryptographic Accelerator Hard IPs.
  3. Configure the IP as described in Specifying the IP Parameters and Options or update the register bits in the configuration block of the AXI-Lite interface.
  4. Start creating the packets in a format specified during the IP parameter configuration.
  5. Stream in the packets.
  6. Collect the packets streamed out from the AES/SM4 Inline Cryptographic Accelerator and send them to your logic.
  7. Stop sending packets to the Symmetric Cryptographic Accelerator Hard IP if any error signal asserts in the AXI-ST interface.
  8. Handle the error received in the AXI-ST interface, if applicable.
    Note: The error handling is out of scope of the Symmetric Cryptographic Accelerator Hard IP.
  9. Then, assert the subsystem_cold_rst_n signal and reprogram the Symmetric Cryptographic Accelerator Hard IP registers for the desired configuration. Next, deassert the subsystem_cold_rst_n signal and start streaming packets again.