8.8.3. Steps to Run the Design Example on Hardware

This section provides the steps for running the design in hardware:

Program the device via the JTAG programmer.
Open a Windows command prompt or a Linux terminal.
Navigate to the directory containing the quartus_py executable (quartus_py.exe in Windows or quartus_py in Linux). The directory in Windows looks similar to the following path:
C:\altera_pro\25.3\qprogrammer\quartus\bin64\
Run the quartus_py executable to execute IPython, an open-source Python shell. For more information about IPython refer tohttps://ipython.org. Use one of the following Windows commands to open a Python console:
- C:\altera_pro\25.3\qprogrammer\quartus\bin64\quartus_py.exe -m IPython
- C:\altera_pro\25.3\qprogrammer\quartus\bin64\quartus_py.exe --interactive_shell
At the Python prompt, import the Python package required to run the tests by entering the following command:
import pysv_fpga.fmica.run_fmica as rf

The import Python command brings the package pysv_fpga.fmica.run_fmica into the current interactive shell Python scope. This command also gives the package a short alias of rf which can be used to refer to the package without typing its entire fully-qualified name.
Use the function rf.start to tell the Python subsystem which version of System Console you use and what .sof is to be programmed into the FPGA.

The .sof is the same .sof generated when you compiled the example design. This command is similar to the following:
rf.start(r"C:\altera_pro\25.3", r"C:\Users\fm71_crypto\design\example_design.sof")
The leading r in the syntax r"C:\altera_pro\25.3" indicates that the string in quotes is a "raw" string. The backslash (\) characters in the raw string are interpreted as literal backslashes and do not need to be escaped.

This is particularly important in Windows, where the directory separator is a backslash. The first argument to this function is the version of System Console to be used as specified by the ACDS directory location. The second argument is the compiled .sof file to be programmed into the FPGA.
To see the list of tests available, enter: tests = rf.available_tests()

This returns a list of strings containing the names of the YAML files that drive the available tests. There are nine YAML files known to the Python script. Each YAML file represents one of the Example Design configurations.

The locations of the YAML files are known to the quartus_py script, so only the file name needs to be supplied.
To run the test, use the rf.run_test method. The argument to the method is the YAML file name, either from the previously stated variable or as a string. Examples of these two methods:
```
rf.run_test(tests[1],“verbose”)
rf.run_test(“<test name>.yml”, “verbose”)
```
Note: Python lists are indexed starting at 0, so the syntax tests[1] really indicates the second test in the list.
1. Type help(rf.run_test) to print out details of the run_test function.
2. Type rf.available_tests() to list all the available tests.

The test runs and produces a log file of its output. The verbose argument is optional. If it is included, the test produces diagnostic output and puts the output in the log file. If it is omitted, a much shorter output log is produced.

Note: The Python script that runs the tests uses System Console as an API for communicating with the FPGA. When the Python script runs, it automatically invokes the System Console. The System Console window displays. Communication between the host computer and the FPGA JTAG port from the Python script does not echo in the System Console window.

The script outputs the log file in the directory containing the pysv_fpga.fmica.run_fmica package, in a subdirectory called fmica_vsip_test_logs.

The test log indicates the status of the data generated and received by the VSIP.

The following is an example of the beginning of a typical log file with the verbose option:

[2022-07-08 11:36:02,948] [INFO    ] Command line args: ['--config_file',
'C:\\Users\\jojones\\Crypto_example_design\\customer_tests\\GCM_256_AES.yml',
'+sof','-jtag', 'C:\\Users\\jojones\\Crypto_example_design\\example_design.sof'][2022-07-08 11:36:02,952] [INFO    ] No web power cycle 
[2022-07-08 11:37:02,026] [INFO    ]

#####################################################

[2022-07-08 11:37:02,493]  [INFO    ] VSIP mode for fpga0.jtag.fmica_vsip0 is 0 
[2022-07-08 11:37:02,496]Q [INFO    ] Total Iteration count:1
[2022-07-08 11:37:02,498]  [INFO    ]

#####################################################

[2022-07-08 11:37:02,500]  [INFO    ] Loop iteration number: 1        
[2022-07-08 11:37:02,502]  [INFO    ]

####################################################

[2022-07-08 11:37:02,504]  [INFO    ] config files
C:\Users\jojones\Crypto_example_design\customer_tests\GCM_256_AES.yml
[2022-07-08 11:37:02,836]  [INFO    ] Created config object sucessfully for
the file: C:\Users\jojones\Crypto_example_design\customer_tests\GCM_256_AES.yml

[2022-07-08 11:37:02,836]  [INFO    ] Created config object sucessfully for
the file: C:\Users\jojones\Crypto_example_design\customer_tests\GCM_256_AES.yml

[2022-07-08 11:37:02,864]  [INFO    ] Resetting HIP:fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:02,868]  [INFO    ] Resetting Tx: fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:02,870]  [INFO    ] Resetting Rx: fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:02,872]  [INFO    ] Resetting axi_st: fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:02,937]  [INFO    ] Flushing the global control register:
vsip.path = fpga0.jtag.fmica_vsip0 register value = 0x40000004

[2022-07-08 11:37:02,874]  [INFO    ] Resetting axi_lite: fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:02,945]  [INFO    ] Deasserting resets: fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:03,011]  [INFO    ] Flushing the global control register:
   vsip.path = fpga0.jtag.fmica_vsip0 register value = 0x40760004

[2022-07-08 11:37:03,125]  [INFO    ] load_ctrl_stats asserted: vsip.path =fpga0.jtag.fmica_vsip0 register value = 0xc0760004

[2022-07-08 11:37:03,237]  [INFO    ] load_ctrl_stats deasserted: vsip.path
     = fpga0.jtag.fmica_vsip0 register value = 0x40760004

[2022-07-08 11:37:04,464]  [INFO    ] register_reset_verify returned true:
vsip.path = fpga0.jtag.fmica_vsip0 register value = 0x40760004

[2022-07-08 11:37:04,474]  [INFO    ] Configuring vsip fpga0.jtag.fmica_vsip0

[2022-07-08 11:37:04,503]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring
the field intrlv_mode of register fpga0.jtag.fmica_vsip0.global_control to 1

[2022-07-08 11:37:04,584]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
field stop_on_stat_err of register fpga0.jtag.fmica_vsip0.global_control to 0

[2022-07-08 11:37:04,656]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
field stop_on_int_err of register fpga0.jtag.fmica_vsip0.global_control to 0

[2022-07-08 11:37:04,731]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
field run_typ of register fpga0.jtag.fmica_vsip0.global_control to 0

[2022-07-08 11:37:04,838]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
field en of register fpga0.jtag.fmica_vsip0.tx0.ingress_control to 1

[2022-07-08 11:37:04,922]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring
the field algo_typ of register fpga0.jtag.fmica_vsip0.tx0.ingress_control to 0

[2022-07-08 11:37:05,005]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the 
field key_typ of register fpga0.jtag.fmica_vsip0.tx0.ingress_control to 1

[2022-07-08 11:37:05,086]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring
thefield flw_typ of register fpga0.jtag.fmica_vsip0.tx0.ingress_control to 0

[2022-07-08 11:37:05,188]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring
thefield frms_to_send of register fpga0.jtag.fmica_vsip0.tx0.no_of_frms to 10

[2022-07-08 11:37:05,302]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
 field aad_len of register fpga0.jtag.fmica_vsip0.tx0.aad_len to 16

[2022-07-08 11:37:05,415]  [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
 field txt_len of register fpga0.jtag.fmica_vsip0.tx0.text_len to 256

[2022-07-08 11:37:05,532]   [INFO    ] fpga0.jtag.fmica_vsip0 configuring the
field byp_len of register fpga0.jtag.fmica_vsip0.tx0.bypass_len to 16

At the end of the log file, which displays at the end of the output in the terminal window, you can see an indication that the test passed. The following log output indicates a passed text:

##################################################

[2022-07-08 11:38:11,678]   [INFO    ] End of run_vsips function . Overall
Status: TEST_PASS , Out of 1 loops , 1/1 passed and 0/1 failed 
[2022-07-08 11:38:11,682]   [INFO    ] System exit is 0

8.8.3. Steps to Run the Design Example on Hardware - 2025-12-16

Symmetric Cryptographic Accelerator Hard IP User Guide